Security Coverage: Assuring Comprehensive Security in Hardware DesignAs hardware systems become increasingly complex and security…Read More
Scaling 3D IC Technologies – Siemens Hosts a Meeting of the Minds at DAC3D IC was a very popular topic at…Read More
Analysis and Exploration of Parasitic EffectsWith advanced semiconductor processes continuing to shrink, the…Read More
Siemens Proposes Unified Static and Formal Verification with AIGiven my SpyGlass background I always keep an…Read More
Alchip Launches 2nm Design Platform for HPC and AI ASICs, Eyes TSMC N2 and A16 RoadmapAlchip Technologies, a global leader in high-performance computing…Read More
-US, Japan & Dutch agree to embargo some China chip equip
-Goes beyond just leading edge & will increase negative impact
-China might catch up in decades or invade Taiwan tomorrow
-Why the memory downturn could be longer than expected
It appears that the US has put together a coalition of the US, Japan and… Read More
On big chip design projects the logic verification effort can be larger than the design effort, taking up to 70% of the project time based on data from the 2022 Wilson Research Group findings. Sadly, the first silicon success rate has gone downwards from 31 percent to just 24 percent in the past 8 years, causing another spin to correct… Read More
For a leading-edge lithography technology, EUV (extreme ultraviolet) lithography is still plagued by some fundamental issues. While stochastically occurring defects probably have been the most often discussed, other issues, such as image shifts and fading [1-5], are an intrinsic part of using reflective EUV optics. However,… Read More
-Lam Research chops guidance, outlook & headcount sharply
-Further declines as 2023 will be H1 weighted- No end in sight
-System sales cut by more than half as even service is cut
-Memory is the culprit as expected-Forcing business “reset”
While Lam reported a good December,… Read More
Together with our R&D partner CEA-Leti, we recently completed an environmental initiative in which we analyzed the environmental impact of Weebit’s Resistive Random-Access Memory (ReRAM / RRAM) technology compared to Magnetoresistive Random Access Memory (MRAM) – another emerging non-volatile memory (NVM) technology.… Read More
Amid the tumult of SoC design advances and accompanying verification and implementation demands, it can be easy to forget that all this activity is preceded by architecture design. At the architecture stage the usual SoC verification infrastructure is far too cumbersome for quick turnaround modeling. Such platforms also tend… Read More
Nearly every week I read in the popular press another story of a major company being hacked: Twitter, Slack, LastPass, GitHub, Uber, Medibank, Microsoft, American Airlines. What is less reported, yet still important are hardware-oriented hacking attempts at the board-level to target a specific chip, using voltage Side-Channel… Read More
Colin Alexander ( Director of product marketing at Achronix) released a webinar recently on this topic. At only 20 minutes the webinar is an easy watch and a useful update on data traffic and implementation options. Downloads are still dominated by video (over 50% for Facebook) which now depends heavily on caching at or close to … Read More
Atiq Raza, well known in the semiconductor industry, has observed that “there will be no simple chips below 16nm”. By which he meant that only complex and therefore high value SoCs justify the costs of deep submicron design. Getting to closure on PPA goals is getting harder for such designs, especially now at 7nm and 5nm. Place and… Read More
Dan is joined by Priyank Shukla, Staff Product Manager for the Synopsys High Speed SerDes IP portfolio. He has broad experience in analog, mixed-signal design with strong focus on high performance compute, mobile and automotive SoCs and he has a US patent on low power RTC design.
Dan explores the use of high-speed SerDes with Priyank.… Read More
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