TSMC’s photonics strategy is centered on integrating optical input-output with advanced logic, rather than selling conventional optical transceivers as standalone products. The company is developing a silicon-photonics foundry platform and a packaging architecture called TSMC-COUPE, or Compact Universal Photonic … Read More
Managing Power, Performance and Reliability in the Chiplet EraNext-gen AI accelerators, high-performance processors, and complex computing…Read More
Siemens and TSMC push AI deeper into chip designSiemens and TSMC are expanding their collaboration on…Read More
Agentic AI Can Reach GDS. What Must It Prove Before Engineers Trust It for Tapeout?Agentic AI is beginning to move semiconductor engineering…Read More
TSMC OIP Ecosystem Forum 2026: Opening RemarksThe 2026 TSMC Open Innovation Platform (OIP) Ecosystem…Read More
LLM-assisted schematic test-report analysis and root-cause investigationBy Piyush Bag Intro: In this AI era,…Read MoreIntel Eyes a Memory Comeback as AI Rewrites Chip Economics
Intel is considering a return to memory technology decades after abandoning mainstream DRAM and, more recently, selling its NAND business. Chief executive Lip-Bu Tan has argued that memory should no longer be viewed simply as a low-margin commodity. Artificial intelligence is turning bandwidth, latency and data movement … Read More
Agentrys Shows You How to Build a Multi-Agent System in 30 Minutes
Agentrys believes that a purpose-built multi-agent system for chip design shouldn’t be a quarter-long project. Agentic AI systems are becoming quite popular to cut design time and increase quality for complex chip design projects. The challenge is finding the right agentic flow for a particular application. There are… Read More
Reducing EUV Exposure Dose Through Underlayer Engineering
Extreme-ultraviolet lithography is essential for manufacturing advanced semiconductor devices, but its continued scaling presents a difficult materials problem. Photoresists must simultaneously provide high resolution, low exposure dose, limited line-edge or linewidth roughness, and extremely low defectivity. … Read More
CEO Interview with Ajit Prabhu of Quest Global
Ajit Prabhu is the Co-Founder and CEO of Quest Global, a global engineering services company driven by a single purpose: to be the most trusted partner for solving the world’s hardest engineering problems. Under his leadership, Quest Global has built long-term, sustainable partnerships and delivers end-to-end engineering… Read More
Questa One Updated at DAC 2026
Abhi Kolpekwar, VP & General Manager, Digital Verification Technologies at Siemens EDA met with me at #DAC2026 to provide the big picture on smart verification tools, something they call Questa One. Their verification tools are infused with AI to improve productivity on projects like SoCs, 3D IC and chiplets. Abhi shared… Read More
The Twelve-Month Rule Does Not Describe a New Fab
By Nikhil Shah
Capital spending is often treated as if it becomes semiconductor capacity about twelve months later. That can be a useful rule for equipment installed in an existing fab. It is a poor description of a new fab built from the ground up.
I tested the distinction using five advanced-node projects in the United States where… Read More
CEO Interview with Sumeet Kumar of Innatera
Dr. Sumeet Kumar is CEO of Innatera, the pioneering Dutch neuromorphic processor company. Dr. Kumar was previously with Intel and Indrion Technologies, and has spent his career in microprocessor development. He co-founded Innatera in 2018 as a spin off from the Delft University of Technology.
Tell us about your company?
When… Read More
The Fab Is Not the Finish Line
AI may close the design. The fab may finish the silicon. Production still has to realize the system.
Semiconductor engineering is becoming extraordinarily capable.
EDA platforms are expanding from individual design tasks toward increasingly complete system analysis.
Multiphysics simulation is connecting electrical, … Read More
Hot Chips 2026: Architectures for the Agentic Computing Era
Hot Chips 2026, formally the thirty-eighth Symposium on High Performance Chips, arrives at Stanford’s Memorial Auditorium from August 23 through 25 with a program that captures a decisive shift in computer architecture. Peak arithmetic throughput remains important, but the conference is increasingly about system balance:… Read More


The Invisible Bottleneck Is Costing You Time You Can’t Get Back