Electrical copper interconnects, once the backbone of data center networks, are facing growing challenges. Rapid expansion of AI and ML applications is driving a significant increase in cluster sizes within data centers, resulting in substantial demands for faster I/O capabilities. While the surge in I/O requirements is … Read More


Podcast EP188: The New Demands for Memory Design and the Synopsys Approach with Anand Thiruvengadam
Dan is joined by Anand Thiruvengadam, director of product and business management and head of the Solutions and Go-to-Market functions for the memory market segment at Synopsys.
Anand discusses the substantial demands experienced by memory designers due to trends such as big data analytics. He describes how these demands impact… Read More
ASML- Longer Deeper Downcycle finally hits lithography – Flat 2024 – Weak Memory – Bottom?
- ASML reports in-line QTR but future looks flat for 2024
- Downcycle finally hits litho leader- ASML monopoly solid as ever
- Memory remains bleak – New China sanctions unclear
- Recovery timing is unclear but planning for an up 2025
In Line Quarter and year as expected
Overall revenues came in at Euro6.7B with EPS at Euro4.81, more… Read More
CEO Interview: Pat Brockett of Celera
Pat Brockett is a veteran of the global semiconductor industry. He began his career in sales and marketing at Texas Instruments. After that, he was senior vice president of worldwide sales and marketing at National Semiconductor. Subsequently, he headed the analog division and is credited with turning it around.
Later, he was… Read More
The Path to Chiplet Architecture
If you have anything to do with the semiconductor industry, you already know that one of the hottest areas for both manufacturing and EDA are systems designed with advanced packaging, basically putting more than one die (aka chiplets) in the same package.
When 3D packaging was first introduced, there were not really any effective… Read More
IEDM 2023 is Coming in December
Anyone who has read my previous IEDM articles will know I view it as one of the best conferences on semiconductor process technology. From the tutorials, short courses and the conference papers there are so many great opportunities to keep up to date on the latest developments. The following are the conference organizers’ announcements… Read More
An Update on IP-XACT standard 2022
Semiconductor IP design re-use has enabled the relentless growth in complexity of SoC and chiplet-based systems over the years, and with IP reuse comes many unique challenges. Fabless design companies use IP provided by a vibrant ecosystem of IP suppliers and foundries, plus internal re-use in the quest to get to market more … Read More
Analog Bits Leads the Way at TSMC OIP with High-Accuracy Sensors
The 15th TSMC Open Innovation Platform® (OIP) event was held recently. This event is a focal point across the industry for cutting-edge development and industry-level collaboration. Appropriately, advanced packaging, paving the way for multi-die design was a focal point for the event. You can get a good overview of what was … Read More
ASML- Absolutely Solid Monopoly in Lithography- Ignoring hysteria & stupidity
- This past weeks over-reaction to Canon echoes the Sculpta Scare
- Nanoimprint has made huge strides but is still not at all competitive
- Shows basic lack of understanding of technology by some pundits
- Chip industry has been searching for alternatives that don’t exist
Much ado about nothing much…..
This past week we … Read More
Qualcomm Insights into Unreachability Analysis
Unreachability (UNR) analysis, finding and definitively proving that certain states in a design cannot possibly be covered in testing, should be a wildly popular component in all verification plans. When the coverage needle stubbornly refuses to move, where should you focus testing creativity while avoiding provably untestable… Read More
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