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Semiconductor Expert Forum

Video EP5: A Discussion of Photonic Design Challenges and Solutions with Keysight

Video EP5: A Discussion of Photonic Design Challenges and Solutions with Keysight
by Daniel Nenni on 05-16-2025 at 6:00 am
Categories: EDA, Keysight EDA

In this episode of the Semiconductor Insiders video series,  Dan is joined by Muhammad Umar Khan, Product Manager for Photonics Design Automation Solutions at Keysight Technologies. Muhammad describes the primary design challenges of photonic design with Dan. These include accurate models and a uniform methodology… Read More

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CEO Interview with Thar Casey of AmberSemi

CEO Interview with Thar Casey of AmberSemi
by Daniel Nenni on 05-16-2025 at 6:00 am
Categories: AI, CEO Interviews

AmberSemi CEO Thar Casey

Thar Casey is a serial entrepreneur, focused on disruptive, game changing technology architecture. Today, he is the CEO of AmberSemi, a young California-based fabless semiconductor company advancing next-generation power management (conversion, control and protection) that revolutionizes electrical products and semiconductor… Read More

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EDA AI agents will come in three waves and usher us into the next era of electronic design

EDA AI agents will come in three waves and usher us into the next era of electronic design
by Admin on 05-15-2025 at 10:00 am
Categories: AI, EDA, Siemens EDA

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Author: Niranjan Sitapure, AI Product Manager, Siemens EDA

We are at a pivotal point in Electronic Design Automation (EDA), as the semiconductors and PCB systems that underpin critical technologies, such as AI, 5G, autonomous systems, and edge computing, grow increasingly complex. The traditional EDA workflow, which includes… Read More

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Webinar – Achieving Seamless 1.6 Tbps Interoperability with Samtec and Synopsys

Webinar – Achieving Seamless 1.6 Tbps Interoperability with Samtec and Synopsys
by Mike Gianfagna on 05-15-2025 at 6:00 am
Categories: AI, Events, Samtec, Semiconductor Services, Synopsys

Webinar Achieving Seamless 1.6 Tbps Interoperability with Samtec and Synopsys

It is well-known that AI is upending conventional wisdom for system design. Workload-specific processor configurations are growing at an exponential rate. Along with this is an exponential growth in data bandwidth needs, creating an urgency for 1.6T Ethernet. A recent SemiWiki webinar dove into these issues. Synopsys and … Read More

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Safeguard power domain compatibility by finding missing level shifters

Safeguard power domain compatibility by finding missing level shifters
by Admin on 05-14-2025 at 10:00 am
Categories: EDA, Siemens EDA

fig1 missing level shifters

In the realm of mixed signal design for integrated circuits (ICs), level shifters play a critical role for interfacing circuits that operate at different voltage levels. A level shifter converts signal from one voltage level to another, ensuring compatibility between components. Figure 1 illustrates a missing level shifter… Read More

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A Timely Update on Secure-IC

A Timely Update on Secure-IC
by Bernard Murphy on 05-14-2025 at 6:00 am
Categories: AI, Automotive, Secure-IC, Security

Semi value chain

I last wrote about Secure IC back in 2023, a provider of embedded security technologies and services. Cadence announced at the beginning of 2025 their intention to acquire this company, which warrants a check-in again on what they have to offer. Secure-IC addresses multiple markets, from automotive, through defense/space and… Read More

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The Journey of Interface Protocols: The Evolution of Interface Protocols – Part 1 of 2

The Journey of Interface Protocols: The Evolution of Interface Protocols – Part 1 of 2
by Lauro Rizzatti on 05-13-2025 at 10:00 am
Categories: AI
2 Comments

The journey of interface protocols part 1 table 1

Prolog – Interface Protocols: Achilles’ Heels in Today’s State-of-the-art SOCs

June 30 was only a week away when Varun had a sleepless night. The call from the datacenter manager the evening before alerted him on a potential problem with the training of a new Generative AI model. Six months earlier Varun’s employer installed… Read More

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Leveraging Common Weakness Enumeration (CWEs) for Enhanced RISC-V CPU Security

Leveraging Common Weakness Enumeration (CWEs) for Enhanced RISC-V CPU Security
by Kalar Rajendiran on 05-13-2025 at 6:00 am
Categories: Analytics, Cycuity, EDA, RISC-V, Security

Information Flow Analysis Cycuity's Unique Approach

As RISC-V adoption accelerates across the semiconductor industry, so do the concerns about hardware security vulnerabilities that arise from its open and highly customizable nature. From hardware to firmware and operating systems, every layer of a system-on-chip (SoC) design must be scrutinized for security risks. Unlike… Read More

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Metal fill extraction: Breaking the speed-accuracy tradeoff

Metal fill extraction: Breaking the speed-accuracy tradeoff
by Admin on 05-12-2025 at 10:00 am
Categories: EDA, Siemens EDA

fig1 metal fill

As semiconductor technology scales and device complexity increases, accurately modeling the parasitic effects of metal fill has become critical for circuit performance, power integrity, and reliability. Metal fill is a crucial part of the manufacturing process, ensuring uniform layer density, improving planarization,… Read More

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How Arteris is Revolutionizing SoC Design with Smart NoC IP

How Arteris is Revolutionizing SoC Design with Smart NoC IP
by Mike Gianfagna on 05-12-2025 at 6:00 am
Categories: Arteris, Events, IP

How Arteris is Revolutionizing SoC Design with Smart NoC IP

Recently, Design & Reuse held its IP-SoC Days event at the Hyatt Regency in Santa Clara. Advanced IP drives a lot of the innovation we are seeing in chip design. This event provides a venue for IP providers to highlight the latest products and services and share a vision of the future. IP consumers are anxious to hear about all the… Read More