System Validation Engineer to Staff Engineer

The Role:

As a RISC-V System Validation Engineer in the CoreIP team, you will develop, deploy, and support emulation and/or FPGA environments. You will collaborate with cross-functional disciplines to define emulation test strategy, define test-frameworks, implement test-plans, and debug complex emulation hardware, software, and silicon design issues.

Responsibilities

• Bring up Silicon designs on FPGA platforms, root causing design, test and emulator environment issues failures.
• Collaborate with cross-functional teams on developing and implementing emulation strategies based on product goals.
• Establish key hardware and software on emulation to establish readiness for silicon and software bring-up.

Requirements

• Solid understanding of processor and SoC architecture, or a strong desire and ability to learn the same.
• Above 3 years direct system development, validation and debugging on FPGA platform experience
• Ability to debug processor designs on FPGA platforms.
• The experience for linux-based open source software development.
• A conscientious and thorough approach to Design Verification and System Validation.
• A thorough understanding of the high-level verification flow methodology (test plan generation, test generation, failure analysis, coverage analysis, and closure).
• Good interpersonal skills to listen to diverse points of view and influence people from different disciplines.
• An unwavering dedication to product quality
• Familiarity with and/or ability to learn languages and methodologies that are not part of the industry-standard approach to verification (Scala, Chisel, etc.).