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An update here: https://frederickchen.substack.com/p/stochastic-pupil-fill-in-euv-lithography, particularly relevant to Stochastic Effect of Large Pupil Fill.
As a substrate/package designer engineer, you will collaborate in designing and developing solutions for our semiconductor portfolio. Reporting to the Back End Lead, you will collaborate with the SoC Top Team and the Backend Team to create complex substrate designs that need to deal with high frequency signals, performance requirements and customer expectations.
What do we offer? Flexible work schedules, competitive pay, a highly learning environment and opportunities for advancement. Come and join us in the beautiful city of Barcelona!. Candies, coffee and free spanish lessons included!. (**Visa sponsorship if required**)
Requirements
Experience in signal integrity and signal conditioning
Experience in high frequency communications (like Ethernet)
Experience in bump map design
Experience in organic substrate stacks (Metal Layers characteristics, bump pitch,…)
Experience in power distribution
Proven fundamentals in the electrical/material/thermal or mechanical engineering field(s)
Good knowledge of the unix environment, scripting languages (Python, TCL, shell) and scripting automation methodology
Understanding in some signal integrity/power integrity tools (XtractIM, PowerSI, HFSS, Q3D, etc.) and package model extraction
Strong problem-solving skills and attention to detail
An update here: https://frederickchen.substack.com/p/stochastic-pupil-fill-in-euv-lithography, particularly relevant to Stochastic Effect of Large Pupil Fill.
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