Senior Engineer II – AMS Behavioral Modeling

In this job you will be responsible for translating custom mixed-signal circuit schematics into efficient SystemVerilog / Verilog behavioral models for higher level simulations. You will have to closely interact with circuit design teams to understand fine details of custom circuits, and with DV teams for effective verification. You will have to run various simulations and equivalence checks to ensure that the model matches closely with the custom circuits. You will have to handle the quality of such models for production worthiness across projects. Documenting results and verification procedures, participating in periodic reporting, design reviews, internal seminars and training sessions.

What you’ll do

As an Engineer in IP Modeling team, candidate would be responsible for analyzing and modelling analog circuit behaviour (System Verilog/Verilog modelling) at Alphawave Semi:

• Good understanding of analog concepts and circuits
• Develop verification test benches, and pioneering methodologies suitable for the Analog IP
• Collaborate across different business units, application engineers, designers
• Document or otherwise archive developed material for future use or re-use

What you’ll need

• Bachelors or Masters in Electrical/Electronics Engineering with minimum 3-4 years of proven experience
• Experience in developing behavioral models for Analog blocks like I/Os, PLL, Delay Line, DCC, Bandgap, Oscillators etc using verilog/systemverilog
• Functional understanding of mixed signal / analog IPs (as above) for modelling
• Experience in writing self-checking Test-benches /Test-Plans for Behavioural models, debug, review and documentation
• Excellent knowledge of digital logic gates, clocking and state elements
• Hands-on and exposure to Synopsys-VCS, Cadence-Xcelium and waveform viewers like Simvision, Verdi, etc.
• Good understanding of Digital Logic and Finite State Machines. (Derive state machine from functional descriptions of analog block to develop behavioral model for same)
• Some understanding of SPICE circuit simulations
• Basic knowledge of reading device level schematics for analog circuits
• Knowledge of Verilog-AMS, mixed signal simulations and verification is a plus
• Some understanding of scripting languages PERL/Python
• Experience in Linux command-line based environment, Linux commands, and text editors (gvim etc.)
• Fluent English skills are required

As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes:

• Great compensation package
• Restricted Stock Units (RSUs)
• Hybrid Working Model
• Provisions to pursue advanced education from Premium Institute, eLearning content providers
• Medical Insurance and a cohort of Wellness Benefits
• Educational Assistance
• Advance Loan Assistance
• Office lunch & Snacks Facility