Digital Design Engineer

• Develop a thorough understanding of system-level design specifications
• Verilog RTL Coding, Synthesis, Simulation of the digital IPs
• Develop advanced verification environment and test-bench components
• Conduct RTL linting, CDC/RDC checks, and formal verification as part of the sign-off flow
• Perform synthesis, timing analysis, and work with physical design teams on DFT and timing closure
• Hardware verification of the digital module using cutting edge FPGA kits
• Gate level verification of digital IPs

Essential Qualifications and Experience: 

• Bachelor’s degree of: Electronics Engineering, M.Sc. in Electronics Engineering is a plus
• 0-3  Years of experience in VLSI Digital Design/Verification, gate verification techniques is a plus
• Strong knowledge of Verilog RTL design/simulation
• Knowledge of clock domain crossing (CDC) and reset domain crossing (RDC) techniques
• Knowledge of ASIC/FPGA design flows including RTL Synthesis, Place and Route, and Timing Sign-off
• Solid understanding of static timing analysis (STA) and timing constraints (SDC)

Desirable Qualifications and Experience:

• Familiarity with System Verilog, UVM, RTL/gate verification techniques
• Knowledge of Unix/Linux operating system
• Knowledge of shell scripting/programming languages