The 1999 IDM paper Sub 50-nm FinFET: PMOSstarted the 3D transistor ball rolling, then in May of 2011 Intel announceda production version of a 3D transistor (TriGate) technology at 22nm. Intel is the leader in semiconductor process technologies so you can be sure that others will follow. Intel has a nice “History of the Transistor” backgrounder in case you are interested. Probably the most comprehensive article on the subject was just published by IEEE Spectrum “Transistor Wars: Rival architectures face off in a bid to keep Moore’s Law alive”. This is a must read for all of us semiconductor transistor laymen.
My first pick of talks at this month’s Common Platform Technology Forumwill be given by Dr. Greg Yeric, ARM Consultant Design Engineer, R&D. Greg has 20 years of semiconductor experience beginning with Motorola/Freescale, HPL, which brought him to Synopsys through acquisition, and for the last 4+ years he has been at ARM. Greg’s talk “IP Design and the FinFET Transition”will cover foundry access to finFETs. Here is a reprint of an interview with Greg from the Tech Design Forum Newsletter in case you have not seen it:
TDF: What is the big deal about finFETs and what do they mean for IP?
FinFETs hold the promise of being fundamentally better switches than bulk planar transistors. So, they’ll allow favorable power and performance scaling beyond 20nm. However, they are a new kind of transistor with new issues and limitations. They are different enough that one runs the risk of producing sub-optimum IP without good understanding and planning. But properly executed, they’ll mean that 14nm delivers better power and performance.
How big a change are finFETs?
On one hand, they have the same metal-oxide-semiconductor structure, simply folded up, accordion-style, to provide a higher current density. In that sense, designers will see them behave in familiar ways. The key change will be a sizeable bump in the roadmap for some scaling parameters. There’ll be enough notable differences that the transition should offer an opportunity to assess the scaling of our designs.
What specifically should designers be aware of?
Most everyone has heard about quantization – that the finFET drive strength is varied by the number of discrete fins in parallel. For that reason and others, low power designers will face a different granularity in choices than they’ve been used to. Another potentially more interesting side-effect of quantization is a new fin-metal gear ratio. Designers must plan for the fact that finFETs offer a change in the scaling compared to recent nodes. Delay and power can be improved in aggregate, but their components, represented by CV/I and CV^2f, will scale in different ways. I wouldn’t recommend a lazy extrapolation of past trends.
What other differences might there be?
The variability signature will probably change. finFETs improve some aspects of variability but because they have new process components, I’d expect to see other new variation issues. This shift might foretell a change in the balance between local and global variation that will affect memory and logic differently. Also, scaling to 14nm in and of itself won’t be easy, and all of the finFET issues will have to be folded – no pun intended – into this broader context. I’ll discuss a broader process scaling perspective at the forum.
My big question is parasitic extraction of 3D Transistors, how is that going to work?Share this post via: