What really means high reliability for OTP NVM?

Normal operation range for a Semiconductor device is not made equal for systems… If you consider a CPU running inside an aircraft engine control system, this device should operate at temperature ranged between -55°C and +125°C, when an Application Processor for smartphone is only required to operate in the 0°C to +70°C range. When Sidense announce that their OTP macros are fully qualified for -40ºC to 150°C read and field-programmable operations for TSMC’s 180nm BCD 1.8/5V/HV and G 1.8/5V processes, this represent a design challenge probably as difficult to meet that, for example, pushing a Cortex A9 ARM CPU embedded in a 28 nm Application Processor to run at 3 GHz instead of 1.5 GHz.

My very first job was in a characterization department and, even if the technology was CMOS 2 micron, the physics’ laws are still the same today, on a 28 nm or 180 nm technology. Both Temperature and Voltage are used to stress Silicon devices, in order to push it to their operating limits much faster. If you increase ambient temperature, a circuit will operate at lower frequency (and performance), and will be degraded much faster. Increasing the operating voltage will also “help” degrading the chip faster. The type of defects generated by Temperature and Voltage stress are for example:

• Electro-migration, affecting the metal lanes in charge of connecting transistors; the metal atoms are physically moving as a consequence of the Electric field, leading interconnects to break. The temperature acting as an accelerator.

• Oxide breakdown,affect the Silicon thin oxide (SiO2) located between the gate and the channel, at the hearth of the transistor. Both Temperature and Voltage accelerates oxide breakdown. This is a defect in regular transistors, but this effect is also used in a positive way in Non Volatile Memory (NVM), as you will program the memory cell by trapping charges in an isolated location, by breaking the oxide one time, and one time only, so the name One Time Programmable (OTP).

• Leakage current:increasing the ambient temperature will increase the Brownian motion, so the leakage current. Leakage current is usually the first enemy of NVM, because the memory cell capability of retaining charge for a long time has a direct impact on the NVM reliability, the amount of alien charge joining -or leaving- the cell due to leakage current could change the stored value, “0” becoming “1” and reverse. But not for Sidense 1T-OTP NVM cell:

In fact, Sidense 1T-Fuse™ technology is based on a one transistor non-volatile memory cell that does not rely on charge storage, rendering a secure cell that can not be reverse engineered. The 1T-Fuse™ is smaller than any alternative NVM IP manufactured in a standard-logic CMOS process. The OTP can be programmed in the field, during wafer or production testing. In fact, the trimming requirement becomes more important as process nodes shrink due to the increased variability of analog circuit performance parameters at smaller processes, due to both random and systematic variations in key manufacturing steps. This manifests itself as increasing yield loss when chips with analog circuitry migrate to smaller process nodes since a larger percentage of analog blocks on a chip will not meet design specifications due to variability in process parameters and layout.

Examples where trimming is used include automotive and industrial sensors, display controllers, and power management circuits. OTP technology can be implemented in several chips used to build “life critical” systems: Brake calibration, Tire pressure, Engine control or temperature or even Steering calibration… The field-programmability of Sidense’s OTP allows these trim and calibration settings to be done in-situ in the system, thus optimizing the system’s operation. You can implement trimming and calibration of circuits such as analog amplifiers, ADCs/DACs and sensor conditioning. There are also many other uses for OTP, both in automotive and in other market segments, including microcontrollers, PMICs, and many others.

Sidense 1T-OTP has been fully qualified for automotive temperature range, supporting AEC-Q100 Grade 0 applications on TSMC 180nm BCD process. That means that Sidense NVM IP can support applications that require reliable operation and long-life data retention in high-temperature environments. We have seen on the few above examples how Electromigration, Oxyde Breakdown or leakage current can severely impact semiconductor devices under high temperature and/or high voltage conditions. This qualification of Sidense 1T-OTP is a great proof of robustness for this NVM IP design. We can expect the automotive segment chip makers to adopt it, because they have to select a qualified IP, and we also think that chip makers serving other segments should also take benefit of such a robust and proven design, even if they will implement the NVM IP in smaller technology nodes, down to 40 nm.

Eric Esteve from IPNEST

Share this post via:

• 
• 
• 
•