CHERI webinar banner
WP_Term Object
    [term_id] => 178
    [name] => IP
    [slug] => ip
    [term_group] => 0
    [term_taxonomy_id] => 178
    [taxonomy] => category
    [description] => Semiconductor Intellectual Property
    [parent] => 0
    [count] => 1693
    [filter] => raw
    [cat_ID] => 178
    [category_count] => 1693
    [category_description] => Semiconductor Intellectual Property
    [cat_name] => IP
    [category_nicename] => ip
    [category_parent] => 0

IP Challenges, FinFET, 3D-IC, and FD-SOI Updates

IP Challenges, FinFET, 3D-IC, and FD-SOI Updates
by Daniel Nenni on 03-27-2014 at 10:00 am

 Semiwiki is proud to be a sponsor of EDPS 2014:

April 17 & 18, 2014
Monterey Beach Hotel, Monterey, CA

Sponsored by:
IEEE Computer Society of Silicon Valley (CS-SCV)
IEEE Computer Society
Design Automation Technical Committee (DATC)
Council on Electronic Design Automation (CEDA)

The Electronic Design Processes Symposium (EDPS) provides a forum for a cross-section of the top thinkers, movers and shakers who focus on how chips and systems are designed to discuss state-of-the-art electronic design processes and CAD methodologies. The workshop focuses on the improvement of the overall design process, rather than on the functions of the individual tools themselves.

Featuring the following 2014 Keynote Speakers:

  • Chris Lawless – Director, Intel
  • Wally Rhines – CEO, Mentor Graphic
  • Martin Lund – SVP, Cadence

Program includes the following sessions:
Thursday 4/17 Sessions 8:00AM -5:45 PM

  • Design Flow Challenges (including Panel)
  • Pre-Silicon SW Development Platforms
  • Technology Updates – FinFET, 3D-IC, FD-SOI

Thursday 4/17 Dinner Keynote 6:30PM
Wally Rhines, CEO, Mentor Graphics

Friday 4/18: IP Day 8:00AM-3:00PM

  • IP Integration, Design, Reuse (Session)
  • IP Verification and Qualification (Session)

Program includes engineers and key executives from the following companies:
Altera, Intel, Synopsys, Cadence, TSMC, Mentor, eSilicon, Atrenta, and more…

Important Dates:
– Mar. 31 End of Early Registration
– Apr. 17 On-site Registration

See, to see the detailed Program, Registration
information, and news/review of this upcoming event.

This Symposium will be held at the

GOLD Sponsors: eSilicon, Cadence, Arteris, Netapp, Mentor, Atrenta
Session Sponsors: IPextreme, ClioSoft,

More Articles by Daniel Nenni…..

lang: en_US

Share this post via:


0 Replies to “IP Challenges, FinFET, 3D-IC, and FD-SOI Updates”

You must register or log in to view/post comments.