In fact the question could be about your watch, thermostat or other smart appliance, as soon as the “thing” relies on one or more sensors to function. In this case, we are close to call this thing an IoT (or SmarCoT), we just need to add WiFi, BTLE, ZigBee connectivity. Sensors are ubiquitous, integrated into smartphone, automotive, thermostat, home appliances and many more. If you want to define IoT, you should start to list the many things that use sensors. When a “thing” uses sensor(s), a CPU or DSP or combination of both is not far away, to process the sensor raw data. It becomes a “smart thing”. Connecting a smart thing look like a good idea? Just do it and you will have built a SmarCoT (Smart Connected Thing) or IoT!
The next question is which processor to select, especially when the thing will be battery powered, and the electronic system has to be smart in term of power consumption. We are not talking about a device you need to charge every day or even week, rather several weeks. We know for quite a long time that integration is always a good path for low power: moving from external I/Os to internal connections greatly help to save power. Thus, using a CPU IP subsystem that could be integrated into a larger chip sounds good.
Synopsys DesignWare Sensor and Control IP Subsystem is optimized to process the extensive amount of data in sensor fusion applications. The subsystem includes a rich library of off-the-shelf DSP functions supporting filtering, correlation, matrix/vector, decimation/interpolation and complex math operations. Designers can implement these sensor-specific DSP functions in hardware using a combination of native DSP instructions within the EM5D or EM7D processor and tightly coupled hardware accelerators to boost performance efficiency and reduce power consumption by up to 85 percent compared to discrete solutions.
Synopsys has built a real subsystem as you can see on the above picture, integrating ARC CPU (EM4, EM5D, EM6 or EM7D) tailored to the computation needs. A computation hungry application may require using Instruction and Data memory cache, but you can decide to integrate only the right quantity of embedded SRAM. In both cases, the solution will exhibit minimized power consumption, as there is no power hungry internal bus like AMBA AHB or the like. This architecture sounds like a main differentiator when compared with the competition, even when dealing with low performance CPU like ARM Cortex M, for example.
But low power architecture doesn’t mean low capability: this IP subsystem is expected to interface with sensors, thus it offers a full set of tightly coupled peripheral interfaces (see above), including both digital and analog interfaces, as well as a Pulse Width Modulator (PWM) interface. The lower cost is a sensor, the higher DSP manipulations will be needed, and Synopsys proposes various DSP accelerators, either hard wired (EM4 or EM6), either with native instructions for the EM5D and EM7D versions. Even a Floating Point Unit can be added as a licensable option if needed.
Claiming that your solution is low power is one thing, demonstrating this claim in a real case is better!
Synopsys has benchmarked ARC sensor IP subsystem supporting the same 9-D sensor fusion application, in term of cycle counts as well as energy consumption with two competitor solutions. Synopsys IP subsystem is integrated into an ASIC built on 40LP when the X and Y solution are based on standard parts (from well-known microcontroller manufacturers). The cycle count reduction, by a factor of 5 (with competitor X) or 4 with Y, is impressive. Such a 80% reduction in cycle counts, plus the smarter bus free architecture explains why Synopsys solution exhibits more than 85% savings in energy consumption!
In fact, this ARC IP subsystem is like sensors, it’s ubiquitous. It’s not possible to describe in a short paper all the potential configurations ranging from pure RISC CPU, to 25% RISC/75%DSP, passing through any possible implementation. You will get a very good overview, and also some in-depth information by listening this webinar:Share this post via: