Variation-Aware Custom IC Design Best Practices

I’ve worked with Solido for 5 years, and it’s been a pleasure to watch the world’s top semiconductor companies and foundries adopt Solido software for their SPICE simulation flows.

Sub-28nm design starts are accelerating, growing from 150 in 2012 to 900 this year. The move to sub-28nm design nodes is being driven by consumer electronic demands to improve speed, connectivity, reliability, battery life, form factor and cost. For example, according to TSMC data, TSMC 16nm FinFETs versus TSMC 28nm gets 2X gate density, 38% speed improvement at same power, and 54% improved power savings at the same speed.

According to ITRS, threshold voltage variation has increased from 25% in 2005 to 58% in 2013. Threshold voltage variation sources in FinFET transistors are gate length, fin thickness, oxide thickness, random dopant fluctuations, oxide charge and work function. Foundries like TSMC, GlobalFoundries, Samsung and Intel are now providing detailed statistical models in their PDK’s that characterise local (mismatch) and global manufacturing variation data so that designers can get working silicon at suitable yields without having to over-design, taking power, performance and area hits. Since sub-28nm design and implementation cost is more than $100 million, a single design respin can cost over $10 million plus the lost time-to-market product revenue.

The required number of SPICE simulations have increased 10X to 1,000,000X to get the needed design coverage using the advanced node PDK’s, making variation-aware custom IC design tools a standard part of the design flow. While SPICE simulators are focused on fast, accurate and high-capacity simulation, variation-aware custom IC design tools are complementary providing SPICE simulator control and analytics. This enables users to improve design coverage with orders-of-magnitude fewer simulations than brute force for PVT corner analysis, 3-sigma Monte Carlo design and 4- to high-sigma Monte Carlo design. As a result, SPICE simulators together with variation tools are being used in the SPICE simulation flow at advanced nodes.

There is a panel on Variation-Aware Custom IC Design Best Practices at the Design Automation Conference this year. The panel discussion will focus on best practices and methodologies for variation-aware memory, standard cell, analog/RF, and custom digital design. Panel topics will span 4- to high-sigma Monte Carlo verification, high-sigma cell optimization, 3-sigma Monte Carlo verification, verification across 100,000+ PVT/parasitic corners and statistical PVT corners, FinFET variation, variation debug, analog calibration/trimming and SPICE simulation requirements for variation analysis.

Panelists will be Mark Erikson from Broadcom, Jaeha Kim from Seoul National University, Irina Ilatov from Sidense and Trent McConaghy from Solido Design Automation. The panelists have extensive experience developing and deploying variation-aware methodologies in their companies, which should make this an interesting and informative session.
The panel is on DAC Monday and is free to attend. Register for the panel here: https://www.surveymonkey.com/s/6N5LTNC

Panel attendees will be given a complimentary copy of the book written by Paul McLellan and I called Fabless: The Transformation of the Semiconductor Industry.

You can also register for a suite demonstration of Solido Variation Designer software here: http://www.solidodesign.com/page/dac-2014-demo-signup/

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