Going Beyond DRC Clean with Calibre DE

For advanced semiconductor designs, achieving both design rule check clean layouts and optimal electrical performance is crucial for minimizing design iterations, reducing time-to-market and ensuring product reliability. Balancing electrical performance and layout integrity is a difficult task. Achieving an optimal and balanced solution demands deep technical understanding of all the nuances and impact of each set of requirements. There are often unexpected interactions at play. Achieving a result that satisfies all requirements can result in an overly pessimistic design. Pushing the envelope in the other direction can result in a non-functional design.

Siemens Digital Industries Software recently published a comprehensive technical paper on these challenges. It turns out Calibre DesignEnhancer (DE) possesses the required deep understanding of the technology requirements and interactions at play. The product delivers an analysis-based, signoff-quality layout modifying EMIR solution that enhances power integrity and reduces IR drop. This results in improved design reliability and manufacturability across multiple foundry technologies, reduced support costs and increased usability for foundries, CAD teams, and designers. The technical paper gets into substantial detail on how Calibre DE accomplishes this. There are also detailed use cases from Google and Intel. A download link is coming but first let’s explore going beyond DRC clean with Calibre DE.

About the Technical Paper

I find it interesting that Google and Intel are cited side-by-side in this piece. It wasn’t that long ago that Intel would never disclose anything about its design capability and Google would really have nothing to say about chip design. It seems that semiconductor companies are becoming system companies and system companies are becoming semiconductor companies. And so, we move forward.

The technical paper is entitled How Google and Intel use Calibre DesignEnhancer to reduce IR drop and improve reliability. The author is Jeff Wilson. Jeff is a product management director for DFM applications in the Calibre organization at Siemens Digital Industries Software. He is responsible for the development of products that analyze and modify the layout to improve the robustness and quality of the design. Before joining Siemens, Jeff worked at Motorola and SCS. He holds a B.Sc. in design engineering from Brigham Young University and an MBA from the University of Oregon.

About Calibre DE

Foundries face many challenges with each new technology, like the need for new analysis and qualified DRC/LVS decks. Calibre DE addresses this challenge by reading the relevant data from DRC rules file, then using its built-in expertise with SVRF commands to create a deck that modifies the layout to solve identified EMIR problems. These files create a design kit that includes specific DRC values from the foundry/IDM.

At the core of all this is Calibre’s deep understanding of design rules. One example use case is adding DCAP and filler cells after P&R has completed power, performance and area iterations. This can be tricky since P&R tools are not good at filling open spaces with very specific design rules. If you run PV on a medium to large design with DCAP and filler cells inserted by a P&R tool, runtime can exceed 10 hours. Calibre DE Pvr (physical verification ready) flow uses the world’s best correct-by-construction fill tool, SmartFill, to place DCAP and filler cells. The runtime for this approach will take ~1 hour, delivering much better results.

Another example is the challenge of ensuring that designs are free from electrical violations like IR drop. This is getting more important at advanced nodes. Calibre DE Pge (power grid enhancement) and Calibre DE Via (via insertion) are tools that optimize the power delivery network and reduce the impact of IR drop, improving electromigration/IR drop and overall yield. By using these tools, design teams can minimize the risks of power failure and other integrity issues that affect product performance.

The technical paper gets into lots of details about these capabilities and more. You can also access a lot of detailed information on Calibre DesignEnhancer here. Let’s now take a brief look at what Google and Intel found. This information was taken from recent conference presentations from both companies.

Google’s Experience

Google’s goal was to reduce IR drop at 3 nm. The Google team found that finding IR drop issues at the chip finishing stage was particularly challenging and that conventional solutions came with unfortunate consequences:

• Derating means decreased speed.
• Changing floorplan or re-designing the power distribution network (PDN) means additional design cycles.
• Fixing the PDN becomes very complicated and ineffective due to the huge increase in DRC rules, especially if attempted manually or using conventional tools.

Google used Calibre DE via insertion to improve IR drop with little or no timing impact, and Calibre DE power grid enhancement to improve the power grid by creating parallel run lengths. They used the EMIR results to focus layout modifications on design areas where the power grid needed to be enhanced. They also used built-in functionality to limit edits around critical nets and establish priorities for the power signals.

There is a lot more detail on what Google found in the technical paper. You will definitely want to review this data. The figure on the right shows what Google’s flow looks like.

Intel’s Experience

Intel’s goal was to improve power grid robustness at 5nm and beyond. The Intel team had created a PDN during automated floorplanning but found corner cases that prevented some via hookups. The result was a weak power grid and inadequate power hookups that caused inaccurate electrical modeling.

The team provided several nets that needed additional via hookups for Calibre DE Via to work on to maximize the number of vias to reduce IR drop issues. The P&R team did their job based on their understanding of the design rules. They were forced to take a conservative approach to the rules. Using Calibre DE, the P&R team was able to insert an additional 9 million vias on the nets that they specified on the 5 nm process node. These additions were very targeted as shown in the figure below.

By leveraging Calibre DE’s detailed understanding of via-related DRC rules—such as spacing, width and width-dependent rules—Intel was able to insert the additional vias without introducing DRC violations. This significant increase in vias had a measurable impact on IR drop, improving both electrical performance and yield. More details of Intel’s experiences are provided in the publication.

To Learn More

I have just scratched the surface of what is discussed in the new Siemens Digital Industries technical paper, How Google and Intel use Calibre DesignEnhancer to reduce IR drop and improve reliability. If balancing electrical performance and layout integrity at advanced nodes is giving you a headache, you will definitely want to read this paper. You can download your copy here.  And you can learn more about the family of Calibre DE products here.  All this will help you understand going beyond DRC clean with Calibre DE.

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