Key Takeaways
- The transition from monolithic SoCs to chiplet architectures introduces both challenges and opportunities, and Keysight addresses these by focusing on interoperability.
- Keysight is innovating chiplet testing methods away from traditional plugfest approaches, utilizing advanced tools to evaluate both passive and active structures for interoperability.
- Management of complex data in chiplet designs is facilitated by Keysight’s Engineering Lifecycle Management (ELM) tools, promoting integration, traceability, and compliance with industry standards.
Keysight, with deep roots tracing back to Hewlett-Packard, has long been at the forefront of innovation in electronic design and testing. It manufactures electronics test and measurement equipment and software. The company also owns its own foundry and makes custom chips and packages for its instrumentation business. Many may not be aware that it has a long history in electronic design automation (EDA) too and provides advanced solutions for high-speed digital design.
Over the past decade, the shift from monolithic System-on-Chip (SoC) architectures to chiplet-based designs has introduced new challenges and opportunities. Keysight is actively addressing three critical aspects of this transformation: designing for chiplet interoperability, testing for chiplet interoperability, and managing data and IT in a chiplet ecosystem. Nilesh Kamdar, General Manager of Keysight’s EDA division gave a talk at the recent Chiplet Summit 2025.
Designing for Chiplet Interoperability
As the semiconductor industry moves towards a disaggregated model, similar to the early days of the computer industry transitioning away from vertical integration, chiplet-based architectures offer a way to mitigate risk and accelerate time to market. Not every function needs to scale down to the next process node, allowing for a multi-vendor, multi-process ecosystem. Specialization and standardization have helped in scaling chiplet adoption.
Keysight has been actively involved in partnerships to enhance interoperability. One notable example is its work with IP vendor, Alphawave Semi on the Universal Chiplet Interconnect Express (UCIe) standard. By aligning with customer requirements, the company has developed strategies for signal integrity analysis, pre-layout and post-layout modeling, and managing the forwarded clock alongside data transfer.
Another key performance indicator (KPI) that Keysight has focused on in its simulation options for UCIe is the Voltage Transfer Function (VTF). VTF provides valuable insights into crosstalk performance, a critical factor in ensuring reliable chiplet communication. By accurately modeling VTF, engineers can analyze signal integrity and assess potential interference between interconnected chiplets. This makes VTF a key metric for optimizing interoperability and minimizing design risks in complex multi-vendor environments.
Simulating interoperability is key, and Keysight’s expertise in PHY layer analysis plays a crucial role in ensuring seamless communication among various chiplets in a design.
Testing for Chiplet Interoperability
Traditional plugfest testing—where multiple vendors bring devices to verify compatibility, such as in PCIe or USB environments—does not directly translate to the chiplet ecosystem. Instead, Keysight is exploring new strategies to validate chiplet interoperability effectively.
One method involves analyzing passive structures such as Through-Silicon Vias (TSVs), packages, and transmission lines using microprobes and network analyzers for testing which generate S-parameter files as an output . When it comes to active structures, transmitter (Tx) performance can be evaluated using high-end oscilloscopes, while receiver (Rx) validation can leverage a golden reference signal generated by a Bit Error Rate Tester (BERT) to measure response.
Additionally, many chiplets now incorporate on-chip Built-In Self-Test (BIST) mechanisms. While useful, these embedded tests can sometimes be overly optimistic or fail to account for non-linearities. Keysight enhances BIST effectiveness by providing independent, high-precision measurements through oscilloscopes and other test instruments, ensuring accurate calibration and validation.
Data and IT Management in the Chiplet Ecosystem
With chiplet designs introducing greater complexity, managing data across different components and vendors becomes increasingly challenging. Keysight addresses this issue through its enterprise-grade Engineering Lifecycle Management (ELM) tools. These solutions help customers efficiently handle chiplet-related data, ensuring smooth integration and lifecycle tracking. By providing comprehensive data structuring, version control, and real-time collaboration features, these tools enable engineers to maintain design consistency across multi-vendor environments. ELM solutions also enhance traceability, allowing teams to quickly diagnose and resolve design conflicts or interoperability issues. Additionally, Keysight’s approach ensures compliance with evolving industry standards, facilitating smoother adoption of chiplet-based architectures in diverse applications.
Summary
By combining its expertise in test and measurement with advanced data management solutions, Keysight is well-positioned to support the next generation of chiplet-based designs. Its contributions to interoperability, rigorous testing methodologies, and robust IT management solutions are shaping the future of the chiplet revolution, helping the industry transition smoothly from monolithic SoCs to a more flexible and scalable ecosystem.
To learn more about Keysight EDA solutions, visit their product page.
Also Read:
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Chiplet integration solutions from Keysight at Chiplet Summit
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