The motivations for having a data and process management system in place for semiconductor design have existed for a long time. I am reluctant to admit it, but I remember early efforts to do this back in the 80’s at Valid Logic. Cadence was also developing this capability in house through the early 90’s. Back then designs were much smaller; often it would have been enough to get the design work from just one tool under management.
Today designs have billions of transistors, not hundreds of thousands. Also the advent of design platforms necessitates that not only one tool, but completely separate disciplines, such as software, board, packaging, and SOC all be managed together. We live in an age of platforms and complex interdependent development environments.
The development of design and process management has moved out of the tool companies, providing a welcome neutrality for the solutions. But more than that, they have to cover a wider range of activities than any one tool company can offer. That said, many traditional EDA companies are now working in the areas of IP and software development.
Dassualt, after a series of strategic acquisitions, has assembled and developed a comprehensive suite for managing product development. Indeed, I worked for Synchronicity, the original developer of their DesginSync, back in 2000. Dassault acquired that technology when they merged with MatrixOne. On the other end of the spectrum they acquired Pinpoint, used for managing product development, in their merger with Tuscany.
Last week at the Enovia user group meeting in Mountain View I received an update on the Dassault capabilities. Michael Munsey, Dassault’s Director of Semiconductor, Software and IoT Strategy for the Enovia solutions, opened the meeting with an overview of the present day need for the Enovia solutions. In today’s designs, IP is used extensively. IP can be developed internally or externally, but it is important to know its pedigree. Michael cited an example of an export restricted IP that had been used by a design group, which then made available their project as IP for others to use. But the new IP was not marked as export restricted. You can imagine how painful this turned out.
Michael also recalled the days when IP ‘management’ consisted of getting representatives from different groups in a room and doing a show of hands regarding IP use and proliferation. A host of problems can arise: improper royalty billing, missed fixes for critical issues, improper verification flows, etc.
One of Dassault’s main points was that all verification should be tied to a product design specification. And, when specifications change then the verification steps need to be changed to reflect that. A good example of where product verification must be tied to product specification is with ISO 26262, the automobile functional safety standard.
The Enovia tools make the process straightforward by employing a web interface. But their software is designed to be flow aware. Pinpoint can read tool output reports to capture critical metrics on designs. I was impressed to see that the list of things it can capture includes path timing, power, IR drop, and more. Pinpoint is smart enough to read in LEF/DEF so key design status information is made available in a web interface without the need to open up specific design tools, or more importantly expose design data files. Multi-site and multi-company projects can have independent development work, and all the key information in project status is easily shared without exposing the design data itself.
With the advent of more and more platform based designs and the growth in the need for system integration skills, it looks like Dassualt’s Enovia line will be attracting a lot of attention. For more information on the Enovia user group meeting and Dassault’s offerings in this space click here. It was also heartening to see that a few folks who I worked with there in R&D and application support are still there, 15 years later.
Also Read
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Design Collaboration, Requirements and IP Management at #52DAC
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