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Meeting Analog Reliability Challenges Across the Product Life Cycle

Meeting Analog Reliability Challenges Across the Product Life Cycle
by Daniel Payne on 08-14-2018 at 12:00 pm

Create a panel discussion about analog IC design and reliability and my curiosity is instantly piqued, so I attended a luncheon discussion at #55DAC moderated by Steven Lewis of Cadence. The panelists were quite deep in their specialized fields:

  • Elyse Rosenbaum, Professor at the University of Illinois at Urbana. ESD expert, compact modeling, soft failures, IEEE fellow.
  • Mark Porter, Fellow at Medtronics (from my home state of Minnesota).
  • Saverio Fazzari, Booze, Allen and Hamilton, Sr. Technical Advisor to DARPA. HW cybersecurity.
  • L. Balasubramanian, AMS member at TI. AMS SoC integration.
  • Vinod Kariat – VP R&D at Cadence for Spectre and Liberate.


I’ll never forget my first exposure to IC reliability when at Intel we were losing a few percent in yield due to one hot spot on the DRAM layout where I could literally watch under the microscopethe aluminum interconnect start to bubble and dissolve from an excessive current path as I gradually increased the VDD level. We never did resolve what was causing that behavior, and just put our effort into designing the next generation DRAM chip on a new process instead.

The panel format was mostly Q&A, so I’ve captured the gist of most questions raised and how the panelists answered. I’ve been in awe of analog IC designers ever since the foundries started offering FinFET transistors with rather limited quantized widths, all of the modern day layout dependent effects, and reliability concerns like EM, Vt shift, IR drop and variability.

Q: How can I use EDA tools for my military analog requirements?

L. Balasubramanian –TI chips can have high-power requirements. The specs are well understood for analog, but how can I formalize the reliability challenges and DFT issues in the presence of noise. How do I know that I’ve meet all of the requirements, have high fault coverages, yield has low enough DPPM, achieve reliability and perform fault injection analysis? These are where I want more help from EDA tools.

Vinod Kariat –All of the IC reliability challenges have existed for awhile now, but the number of design starts with analog reliability issues (IoT) is just growing faster, and autonomous vehicles require safe electronics with high safety standards.

Q: Who is responsible to figure out what’s going on in analog circuits? Is it the IC designer, reliability engineer or the test engineer?

Saverio – some groups learn how to pass info back and forth between design, reliability and test.

L. Balasubramanian – a quality engineer ensures that every step meets requirements, design and test have to follow the same quality plan. So, it’s not a single person responsible. Even marketing and sales get involved as part of the team to ensure reliability and success.

Mark – all three types of engineers work together throughout the process, even start talking early on to avoid surprises.

Elyse – everyone should collaborate within the Quality Reliability Yield (QRY) groups to meet the ESD issues.

Steve – there is no magic one person expert in all fields, rather collaboration is the norm between team members.

Q: For modeling of ESD and analog defects, do we know what we need to know?

Vinod – for digital test it is well established with fault models from the 1970s, then BIST, etc. On the analog fault side we don’t have a fault modeling standard to establish a baseline. The analog designer would tape out, measure, iterate.

Elyse – for ESD we have a tester that can measure ESD compliance and know how to design for ESD, For other types of reliability we don’t have enough info yet to find all of the defects on each new process node and under all operating conditions, so there’s still a lot of uncertainty right now.

L. Balasubramanian – Yes, for ESD we know how to simulate and measure. For other analog defects we are still learning, but the majority of defects can still be found by modeling with shorts and opens.

Analog tests for functionality against specs, but doesn’t cover aging and other reliability concerns. We need standards for analog test mechanisms.

Q: For Medtronics your environment is well known, so is your reliability design role easier than others?

Mark Porter – It’s not so much about functionality, but for us low-power means ultra-low power which is orders of magnitude beyond standby currents. We cannot afford to drain our implanted batteries to do extra testing modes, so how do we find latent defects early?

Q: For DOD applications what is the expectation of reliability for a small number of chips?

Saverio – the aging question is important to us. For advanced nodes we need a better understanding of the analog failure modes, so that we can analyze this before silicon failures.

Q: What is the number one thing that would help you design more reliable?

Mark – finding latent defects for analog are hard to identify early on.

Elyse – developing a modeling and simulating capability for automotive ESD system analysis.

Saverio – for an older analog design it would be to redesign it more reliably.

L. Balasubramanian – it’s impractical to simulate at SPICE speeds all of the analog defects, so can that somehow be accelerated with a new methodology? Can I get faster models with analog defect behaviors?

Saverio – we would love to use FastSPICE for time reasons, but we don’t trust the accuracy yet.

Q: How is functional safety impacting analog designs?

L. Balasubramanian – analog methodology requirements are similar to digital, because we are finding random defects that happen during the lifetime of the product. We have under-voltage sensors, frequency sensors, but how do you measure jitter on-chip?

Q: How about using redundancy in your system to allow safe failures?

Saverio – safety and resilience are paramount goals for aerospace and military. What can I actually model and simulate?

Mark – in low power we couldn’t use redundancy and still meet our cost and power goals.

Elyse – it’s all about having a mission profile for each project. Each part usage has varying failure modes.

Mark – Intel does a lot of publishing on mission profiles for their chips and systems.

Q: What is Cadence doing for reliability challenges of analog design?

Vinod – Our new reliability tool Legatois used by analog designers for their cells. EMI, EMC and ESD are separated out and handled by different experts. Can we do better analog defect modeling? What are all of the fault mechanisms?

Saverio – the quality of analog transistor data can be suspect from foundry, because it can be too simplified which makes it not realistic enough.

I wasn’t surprised that many of the panelists shared how much they want more automation from their EDA suppliers in order to make analog IC designs more reliable while performing analysis or simulations in a reasonable amount of time. The range of analog circuits is daunting, and I see this area as ripe for new innovations in EDA tools and methodologies.

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