Big Picture PSS and Perspec Deployment

I met Moshik Rubin (Sr. Group Director, Product Marketing and BizDev in the System Verification Group at Cadence) at DVCon to talk about PSS (the Portable Stimulus Standard) and Perspec, Cadence’s platform to support PSS.  This was the big picture view I was hoping for, following more down in the details views from earlier talks.

The standard and supporting tools can do many things but all technologies have compelling sweet spots, something you probably couldn’t do any other way. Moshik provided some big picture answers to this question in what Advantest and Qualcomm are doing today. Both have built bridges in testing objectives, in one case for hardware/software integration, in the other case between pre- and post-silicon testing. Each providing a clear answer to the question: “where is PSS the only reasonable solution?”

Qualcomm automating hardware/software integration testing

Memory-mapped hardware (most hardware these days) interacts with embedded hardware functions (video, audio, AI, etc) through memory-mapped registers. A register has an address in the memory map along with a variety of properties; software interacts with the hardware by writing/reading this address. This interface definition is the critical bridge between hardware and software and must be validated thoroughly.

I remember many years ago system AEs wrote apps to generate these definitions as header files and macros, together with documentation to guide driver/firmware developers. As the design evolved, they would update the app to reflect changes. This worked well, but the bridge was manually built and maintained. As the number of registers and properties on those registers grew, opportunities for mistakes also grew. (One of my favorites, should a flag be implemented as “read” or “clear on read”? Clear on read seems an easy and fast choice but can hide some difficult bugs.)

Qualcomm chose to automate this testing through a single source of truth flow based on PSS and Perspec. They first develop PSS descriptions of use-case scenarios and leaf-level (atomic) behaviors, abstracted from detailed implementation, then develop test realizations (mapping the PSS level to target test engine) for each target. These are a native mode (C running on the host processor interacting with the rest of the SoC), a UVM mode which can interact directly with a UVM testbench, and a firmware reference mode which generates documentation to be used by driver/software developers. As the design evolves, the PSS definition is updated (intentionally, or to fix bugs exposed in regression testing), and all these levels are updated in sync.

Incidentally, I know as I’m sure Qualcomm knows that there are already tools to build register descriptions, header files, and test suites. I see Qualcomm’s approach as complementary. They need PSS suites to test across the vertical range of design applications and to define synthetic tests which must probe system-level behaviors not fully comprehended in register descriptions. Seems like an opportunity for those register tools to integrate in some way with this PSS direction.

This is a big step forward from the ad-hoc support I remember.

Advantest automating pre-/post-silicon testing

Advantest showed a demo of their flow at DVCon, apparently very well attended. Connecting pre- and post-silicon testing seems to be a hot button for a lot of folks. Historically it has been difficult to automate a bridge between these domains. Pre-silicon verification could generate flat files of test vectors that could be run on an ATE tester or in a bench setup, but that was always cumbersome and limited. Now Cadence (and others) have worked with Advantest to directly use the PSS developed in pre-silicon testing for post-silicon validation. The Advantest solution (SiConic) unifies pre-silicon and post-silicon in an automated, and versatile environment by connecting the device functional interfaces (USB, PCIe, ETH) to external interfaces such as JTAG, SPI, UART, I2C, enabling rich PSS content to execute directly against silicon. That’s a major advance for post silicon testing, now advancing beyond post-silicon exercisers in the complexity of tests that can be run, and in helping to help isolate root causes for failures.

I should add one more important point. It seems tedious these days to say that development cycles are being squeezed hard, but for the hyperscalers and other big system vendors this has never been more true. They are tied to market and Wall Street cycles, requiring that they deliver new advances each year. That puts huge pressure on all in-house development, on test development as much as design development. Anywhere design teams can find canned, proven content, they are going to snatch it up. In test they are looking for more test libraries, VIP, and system VIP. Perspec is supported by extensive content for Arm, RISC-V, and x86 platforms, including System VIP building blocks for system testbench generation, traffic generation, performance analysis and score boarding.

You can learn more about Cadence Perspec HERE.