Cadence is Making Floorplanning Easier by Changing the Rules

SoC designs are getting more complex, resulting in a higher level of difficulty to get anything done. This trend is well-known. What I want to focus on here is how to deal with the issue of complexity. There are many approaches to taming this problem — faster algorithms for one, and improved algorithm efficiency or the ability to run on multiple processors are two ways to do that. There are also strategies to integrate algorithms in new ways that provide new perspectives on the problem.  And then there’s the magic of AI/ML. I recently described enhancements Cadence made to the Tempus Timing Signoff Solution that deliver faster timing signoff. This piece discussed how to deploy these last two strategies. What we will discuss here uses none of the above. It is a new approach to solving complexity. Cadence makes floorplanning easier by changing the rules.

This is a remarkable story of innovation. I had the opportunity to speak with Vinay Patwardhan, product management group director in the Digital & Signoff Group at Cadence about the details. Before moving to EDA, Vinay had a career as a design engineer at TI and Sun Microsystems, so he has a deep understanding of design complexity challenges. We started our conversation reviewing some of the basics of floorplanning. This step in the design process has substantial ramifications on downstream implementation. If you start with a good floorplan, things go relatively smoothly and power, performance and area (PPA) objectives are met. If the initial floorplan has shortcomings, which is often the case, you are faced with long iteration loops to converge on a viable design.

As a result, there is a lot of automation deployed early in the design process to try and get the best initial floorplan possible. Vinay explained the traditional approach here. First, macros for the design are placed around the periphery of the chip. Since macros are large blocks that are difficult to move later, they are placed first. Memories, register files or analog blocks are examples of macros. Following macro placement, standard cells are placed in the available area in the interior of the chip. Vinay explained that this approach has some built-in problems with new chip architectures.  Many of these designs do a lot of data acquisition, storage and processing so there are a lot of macros to place. Putting a large number of macros on the periphery creates long wire problems that, in turn, create timing and congestion problems. This makes for a lot of iterations for repair, creating a longer design cycle.

It turns out the main reasons for this macro/standard cell placement process has to do with the limitations of the placer. Vinay explained that typical algorithms use quadratic spatial approaches to divide the available area into sub-regions to solve the two-dimensional standard cell placement problem. So, a “sea of gates” continuous area in the interior of the chip is needed for this to work.

Here is where the conversation got interesting, as Vinay described a way to change the rules of floorplanning. Vinay explained that, if macros are not bound by the limitation to be anchored to the four sides of the available area and are instead allowed to “float”, there is more flexibility for placement algorithms to find an optimal location to a multi-objective optimization problem. He further explained that the new GigaPlace XL engine, within the Cadence Innovus Implementation System, is an extension of the multi-objective standard cell placement GigaPlace engine. GigaPlace XL can handle the placement of macros together with standard cells and I/Os in the same step, concurrently. So, Cadence makes floorplanning easier by changing the rules.

Vinay went on to explain that the Innovus Implementation System is already five years old. About two years ago, Cadence began looking at ways to simultaneously solve the macro/standard cell placement problem. Vinay confessed he was skeptical of this idea at first, having done a lot of complex designs himself. However, after a year of early customer engagements and another year of productization, the solution is here, and it works well. There were some patents filed along the way, too.

We got into some of the details. Macro placement is a combinatorial problem, while standard cell placement is a numerical one. The breakthrough for the GigaPlace XL engine inside Innovus is that, with its solver-based placement technology, it can solve continuous optimization and combinatorial optimization simultaneously. This offers two key benefits:

• Standard cells can be placed on all four sides of the macros, resulting in more resources for timing and wirelength optimization, which leads to improved timing, area, and power
• A slack-aware numerical solver looks at standard cell delays while doing a macro placement, reducing the approximation involved in combinatorial trial-and-error analysis methods, resulting in fewer iterations while delivering a feasible, working floorplan.

Vinay shared a lot of data that details the impact this approach can have. The table, below, summarizes some key metrics.

The PPA improvements are significant. The efficiency improvements shown in the last two columns are quite impressive and really made me take notice. This new technology supports multiple design styles, including advanced node FinFET. There are also well thought out ways to add user control. Vinay stated that customers are already using this new technology to achieve and exceed their PPA targets with a shorter tapeout schedule. Vinay has written a very informative white paper on this approach entitled, “Overcoming PPA and Productivity Challenges of New Age ICs with Mixed Placement Innovation”. You can download your copy here to get the details of how Cadence makes floorplanning easier by changing the rules.

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