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Designing Next Generation Memory Interfaces: Modeling, Analysis, and Tips

Designing Next Generation Memory Interfaces: Modeling, Analysis, and Tips
by Mike Gianfagna on 03-04-2020 at 10:00 am

At DesignCon 2020, there was a presentation by Micron, Socionext and Cadence that discussed design challenges and strategies for using the new low-power DDR specification (LPDDR5). As is the case with many presentations at DesignCon, ecosystem collaboration was emphasized. Justin Butterfield (senior engineer at Micron) discussed the memory aspects and Daniel Lambalot (director of engineering at Socionext) discussed the system aspects. I was able to spend some time with one of the other authors, Zhen Mu (senior principal product engineer at Cadence) as well. Zhen provided background on the tool platform used in this program, which is completely supplied by Cadence.

The LPDDR5 spec was finalized and published last year and is the cutting edge of DDR memory interfaces. Increased speed and lower power don’t come for free. There are many challenges associated with using LPDDR5, including channel bandwidth, reduced voltage margin, the need to route multiple parallel channels, dealing with crosstalk and ensuring proper return currents, multi-drop configurations (2 DRAM loads) and limited equalization capability.

The key features of LPDDR5 can be summarized as follows:

  • Higher data rates (up to 6.4Gbps)
    • Data transfer boosted about 1.5 times of the previous LPDDR4 interface
  • Power-isolated LVSTL interface with:
    • VDD2H=1.05V for the DRAM core
    • VDDQ=0.5V for the I/O
  • New packaging
  • Non-targeted on-die termination (ODT)
  • New eye mask specifications
    • Change from rectangular mask in LPDDR4 to hexagonal mask in LPDDR5
    • Two timing measurements – tDIVW1/tDIVW2 and vDIVW
    • See diagram, below
  • Data bit inversion (DBI)
  • Separate Read strobe (RDQS) and Write strobe (WCK)
  • Advanced equalization technologies such as feed-forward equalization (FFE), continuous time linear equalization (CTLE), and decision feedback equalization (DFE) for the controller and the memory

New eye mask

Timing is one of the most challenging aspects of LPDDR5; controller jitter must be considered. Accurate modeling is key for success. The presentation discussed the details of modeling and analysis approaches to optimize the use of LPDDR5 in actual designs. Items to be considered include device modeling, system-level design with typical topology, channel simulation for parallel bus analysis, bus characterization, modeling filtering functions implemented in LPDDR5 DRAMs and crosstalk simulation.

IBIS (I/O Buffer Information Specification) and the Algorithmic Modeling Interface (AMI) extensions are standards typically used in SerDes design and analysis. IBIS-AMI modeling can also be applied to parallel bus analysis for LPDDR5 designs. The benefits of this modeling approach include interoperability (different models work together), portability (models run in multiple simulators), accuracy (results correlate to measurements), IP protection (circuit details are not exposed) and performance (million-bit simulations are practical).

There are challenges to apply SerDes modeling to a DDR interface, including the non-symmetrical nature of LPDDR5 timing, see diagram below.

LPDDR5 DRAM IV Curves

From a big picture point of view, channel simulations and circuit transient analysis are correlated, including IBIS-AMI models, using the Cadence Sigrity Explorer tool. To complete the analysis, memory models were supplied by Micron and controller models were supplied by the Cadence IP team. Socionext and Micron provided package models for controller and memory, respectively. See diagram below for some results.

IBIS AMI vs. Transient

Green: Circuit simulation; Blue: Channel simulation

For crosstalk simulation, two approaches were used -characterize each bus signal individually as is done in SerDes channel simulations and characterize the entire bus with practical stimulus patterns. Using the following conditions, the effect of channel length on performance can be modeled.

Channel length vs. performance

The analysis suggests a trace length of one inch is desirable. This presentation highlighted the modeling and simulation techniques needed to help achieve a fully functional system with LPDDR5 memories. Accurate modeling with good ecosystem participation are required for success.


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