De-risking RFICs and High Speed SoCs from Electromagnetic Crosstalk

De-risking RFICs and High Speed SoCs from Electromagnetic Crosstalk
by Admin on 09-13-2021 at 12:00 am

Time:
September 13, 2021
8 AM EDT / 1 PM BST / 5:30 PM IST

Venue:
Onlineo

About this Webinar

In today’s near threshold designs, trends like tighter integration and increasing layout density on advanced nodes, frequency escalation (5G) and complex packaging scenarios are making the need for accurate and efficient electromagnetic… Read More


Samtec Lets You Learn from Home with a Great Webinar Lineup

Samtec Lets You Learn from Home with a Great Webinar Lineup
by Mike Gianfagna on 01-20-2021 at 10:00 am

Samtec Lets You Learn from Home with a Great Webinar Lineup

Work from home (WFH) has become a normal occurrence this past year. “Do you work from home?”  “Of course, where else?” Samtec is taking the whole work from home thing up a notch with a new webinar lineup for 2021. Back by popular demand, they are launching a new series of educational webinars. Started last year, the gEEk SpEEk Webinar… Read More


Trace Design for Crosstalk Reduction

Trace Design for Crosstalk Reduction
by admin on 06-25-2020 at 11:00 am

Trace Design for Crosstalk Reduction
Presented by: Scott McMorrow

Returning to basics, we’ll investigate the relationship of trace geometry to crosstalk in interconnect design, and draw some conclusions based on system constraints. Microstrip, stripline, and dual-stripline layer geometries will be examined,

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Designing Next Generation Memory Interfaces: Modeling, Analysis, and Tips

Designing Next Generation Memory Interfaces: Modeling, Analysis, and Tips
by Mike Gianfagna on 03-04-2020 at 10:00 am

IBIS AMI vs. Transient

At DesignCon 2020, there was a presentation by Micron, Socionext and Cadence that discussed design challenges and strategies for using the new low-power DDR specification (LPDDR5). As is the case with many presentations at DesignCon, ecosystem collaboration was emphasized. Justin Butterfield (senior engineer at Micron)… Read More


The Latest in Static Timing Analysis with Variation Modeling

The Latest in Static Timing Analysis with Variation Modeling
by Tom Dillinger on 03-30-2016 at 12:00 pm

In many ways, static timing analysis (STA) is more of an art than a science. Methodologists are faced with addressing complex phenomena that impact circuit delay — e.g., signal crosstalk, dynamic I*R supply voltage drop, temperature inversion, device aging effects, and especially (correlated and uncorrelated) process… Read More