Addressing the Nanometer Digital Design Challenges! (Webinars)

Optimizing logical, physical, electrical, and manufacturing effects, Cadence digital implementation technology eliminates iteration without sacrificing design quality by addressing timing sensitivity, yield variation, and leakage power from the start.

Trends in Digital Design (28nm Design)
Wei Lii Tan, Sr. Product Marketing Manager
Find out what’s needed to be ready for 28nm design – process variation, power-performance-area optimization, DFM considerations, and more.
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Trends in Digital Design (ECOs)
Kenneth Chang, Sr. Product Marketing Manager
Find out what’s needed to handle the increasing complexity of ECOs and their impact on schedule. Leverage a front-to-back automated ECO flow that can help you achieve a 3x gain in productivity and a much faster path to design tapeout.
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Digital Design Technologies
David Stratman, Sr. Product Marketing Manager
Highlights of new physically-aware technologies including physical synthesis and test; new constraint design capabilities including clock-domain-crossing (CDC) checks, low-power ATPG, and precision diagnostics flows; and low-power interoperability support.
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Digital Implementation Technologies
Wei Lii Tan, Sr. Product Marketing Manager
Highlights of new digital implementation technologies including design exploration with automatic macro-placement and flexible models; post-assembly closure for hierarchical implementation; new and improved optimization and clock-tree synthesis (CTS) during block implementation; and the latest mixed-signal capabilities across digital and custom design environments.
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Digital Signoff Technologies
Hitendra Divecha, Sr. Product Marketing Manager
Highlights of standalone and qualified in-design signoff engines for parasitic extraction, physical verification, timing, power-rail integrity analysis, litho hotspot analysis, and chemical-mechanical polishing (CMP) analysis.
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