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28nm Layout Needs Signoff Quality at Design Time

28nm Layout Needs Signoff Quality at Design Time
by Pawan Fangaria on 05-03-2012 at 8:30 pm

We are all aware that at 28nm and below several types of complex layout effects manifest themselves into the design and pose a herculean task, with several re-spins to correct them at pre-tapeout. It’s apparent that the layout needs to be correct by construction at the very beginning during the design stage.

Having worked at Cadence and knowing that it is a leader in layout design tools, I wanted to explore what kind of solution Cadence is providing for these issues. After talking to Dr. Tianhao Zhang, Sr. Product Marketing Manager at Cadence, I was impressed to know that the Cadence product, Virtuoso Integrated Physical Verification System (Virtuoso IPVS), provides a production-proven signoff quality solution to these problems in layout at the design stage.

Virtuoso IPVS integrates foundry-qualified PVS DRC technology into the Virtuoso Layout Suite (available in all tiers L, XL and GXL) in real-time mode to prevent inadvertently created errors, verifies and fixes DRC errors incrementally. The whole system dynamically works on the OpenAccess database, eliminating translations to other formats like Stream, thereby increasing designer productivity multi fold. Furthermore, the PVS in-memory integration works hand-in-hand with the design; the designer doesn’t even need to save the design in order to verify it.

Along with productivity, Virtuoso IPVS provides signoff-level accuracy by using a signoff-quality engine and rule deck. While it employs DRD (Design Rule Driven) editing, preventing errors during layout editing, it provides signoff-level verification of the edits along with surrounding areas on-the-fly. Also, there is in-memory, on-demand verification available for the design as required, hence optimizing design and verification time. As a result, the designer can stay within the Virtuoso Layout System, doing design implementation, verification and signoff, uninterrupted until the design is ready for tapeout.

The Virtuoso IPVS can be used at any node including 20nm where double patterning technology (DPT) takes place. It can detect color loop in real-time based on foundry rules. In addition, Virtuoso IPVS with the Virtuoso unique dynamic colorization feature provides a comprehensive solution at 20nm.

Virtuoso IPVS is being used in production supported by major foundries at advanced nodes. It was pleasing to know from OA database that designers at Cortina Systems, Inc. are using Virtuoso IPVS on 28nm and are seeing great productivity and quality of results with this tool. CDNLive! is a great forum for Cadence customers to present their best stories and experiences in working with Cadence. It was heartening to see the presentation titled “Signoff Quality Verification Earlier in Design Flow with Virtuoso IPVS” at CDNLive! Silicon Valley 2012, presented by Malcolm Stevens, Distinguished Engineer at Cortina Systems. In these slides he discussed the challenges at lower nodes and how the flow with Virtuoso IPVS helps in those difficult situations. More details can be obtained from Dr. Tianhao.

By Pawan Kumar Fangaria
EDA/Semiconductor professional and Business consultant
Email:Pawan_fangaria@yahoo.com


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