WEBINAR: Eliminating Hybrid Verification Barriers Through Test Suite Synthesis

I’ve been following the evolution of the verification space for a very long time including several stints consulting to formal verification companies. It has always been interesting to me to see how so many diverse verification techniques emerge and been used, but without much unification of the approaches. With the emergence and adoption of the Portable Stimulus Standard (PSS), we now have the chance to better unify these approaches in a more meaningful way.

The combined use of simulation and emulation in a verification flow is now commonplace. Many engineering groups have begun augmenting this combination with virtual platforms to create a fully hybrid verification process. This allows for increased capacity and performance, as well as a shift left approach to design architecture and test planning. One barrier remains to a seamless flow between these tools, the fact that each process component requires a different testbench format. Furthermore, improved test content application may significantly accelerate these individual processes.

This webinar will be held in three different time zones starting on August 13, 2019, in the United States,  and will discuss Test Suite Synthesis, where verification scenario intent is described using the new PSS and then synthesized to the respective process implementation. The white box intent description can be used to accelerate UVM block verification, Software Driven Verification (SDV) for SoCs, and prototyping and post-silicon validation, increasing quality while reducing schedules. In addition, this same test description can be used across all these processes, providing a continuous, back and forth flow across the entire verification process. During the webinar you will see a demonstration of the practical application of test suite synthesis on real designs as they progress from architecture to block to SoC, leveraging hybrid verification techniques.

The main portion of the webinar will be presented by Aileen Honess. Aileen has more than 20 years of experience teaching, mentoring, and leading hardware verification projects across a variety of disciplines, companies, and continents. She is an expert in UVM and has recently been assisting those who are modernizing their verification methodology by adopting portable stimulus and portable specifications. After a long career at Synopsys as a lead application specialist in verification, she has assumed the role of Technical Specialist at Breker Verification Systems. She holds a BS in Electrical Engineering from UCLA.

Click here to register for this webinar. Select your time zone to determine which webinar session best fits your schedule. Once registered, you will also receive a few reminders.

About Breker Verification Systems
Breker Verification Systems is the leading provider of Portable Stimulus solutions, a standard means to specify verification intent and behaviors reusable across target platforms. It is the first company to introduce graph-based verification and the synthesis of powerful test sets from abstract scenario models. Its Portable Stimulus suite of tools is Graph-based to make complex scenarios comprehensible, Portable, eliminating test redundancy across the verification process, and Shareable to foster team communication and reuse. Breker’s Intelligent Testbench suite of tools and apps allows the synthesis of high-coverage, powerful test cases for deployment into a variety of UVM to SoC verification environments. Breker is privately held and works with leading semiconductor companies worldwide. Visit www.brekersystems.com to learn more.

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