June 11 in Austin, Texas
- - Includes RISC-V status and tutorial on complex RISC-V verification challenges
- - Lunchtime panel of thought leaders “Addressing Next-Generation RISC-V Verification Needs”
WHO: Breker Verification Systems whose production-proven Trek portfolio solves challenges across the functional verification process for large, complex semiconductors
WHAT: Hosts a seminar titled “Smart Verification Strategies for the Evolving RISC-V Challenge” and a panel featuring RISC-V verification thought leaders for RISC-V developers and engineers looking to understand next-generation verification strategies
WHEN: Wednesday, June 11, from 9:30 a.m. until 1:30 p.m. C.D.T, including lunch
WHERE: Norris Conference Centers Austin, 2525 W. Anderson Lane, Suite 365, Austin, Texas.
Seminar Description
RISC-V represents a major opportunity for the entire semiconductor industry. With this opportunity comes new challenges, one of the most significant being RISC-V core verification. With the advent of more complex RISC-V processors, engineers developing cores or leveraging them in their SoCs must take on new verification scenarios that require different techniques.
The complimentary seminar will describe the status of RISC-V before taking a deep dive into a popular tutorial on a classic complex RISC-V verification example. The session will conclude with a panel of RISC-V verification thought leaders providing their visions over a networking lunch. The event will be interesting to both.
Agenda
9:30 a.m.—Coffee and Networking
10 a.m.—Welcome and Introductions
10:10 a.m.—Overview and Update on RISC-V from Austin Blackstone, RISC-V International Senior Community Marketing Manager
10:40 a.m.—Hypervisor/Paging: An Advanced RISC-V Verification Example Tutorial Parts 1 and 2 with Adnan Hamid, Breker’s CTO
12:20 p.m.—Lunch and Panel “Addressing Next-Generation RISC-V Verification Needs” moderated by Dave Kelf, Breker’s CEO
Panelists:
- Ty Garibay, President of Condor Computing
- Steve Mullinnix, Senior Director, Design Verification at MIPS
- Stephan Gaskins, Fellow, RISC-V Cores with Tenstorrent
About Breker Verification Systems
Breker Verification Systems solves complex semiconductor challenges across the functional verification process from streamlining UVM-based testbench composition to execution for IP block verification, significantly enhancing SoC integration and firmware verification with automated solutions that provide test content synthesis, portability and reuse. Breker solutions easily layer into existing environments and operate across simulation, emulation and prototyping, and post-silicon execution platforms. Its Trek family is production-proven at leading semiconductor companies worldwide and enables design managers and verification engineers to realize measurable productivity gains, speed coverage closure and easy verification knowledge reuse. Its library of SystemVIP test suites addresses common, complex verification scenarios, and includes solutions for RISC-V core and SoC verification, cache and system coherency, and Arm SoCReady validation. Case studies that feature Altera (now Intel), Analog Devices, Broadcom, IBM and other companies leveraging Breker’s solutions are available on the Breker website.
Engage with Breker at:
Website: www.brekersystems.com
Twitter: @BrekerSystems
LinkedIn: https://www.linkedin.com/company/breker-verification-systems/
Facebook: https://www.facebook.com/BrekerSystems/
TrekSoC, TrekSoC-Si, TrekBox and SoC Scenario Modeling are registered trademark of Breker Verification Systems. Breker Verification Systems acknowledges trademarks or registered trademarks of other organizations for their respective products.
For more information, contact:
Nanette Collins
Public Relations for Breker Verification Systems
nanette@nvc.com