I’ve blogged about the Calibre family of IC design tools before:
Smart Fill replaced Dummy Fill Approach in a DFM Flow
Graphical DRC vs Text-based DRC
Getting Real time Calibre DRC Results with Custom IC Editing
Transistor-level Electrical Rule Checking
Who Needs a 3D Field Solver for IC Design?
Prevention is Better than Cure: DRC/DFM Inside of P&R
Getting to the 32nm/28nm Common Platform node with Mentor IC Tools
If you want some hands-on time with the Calibre tools then consider attending the August 25th workshop in Fremont, CA.Share this post via:
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