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DVCon India

DVCon India
by barun on 08-14-2015 at 12:00 pm

 After its successful launch last year, the “Design and Verification Conference & Exhibition India” (DVCon India) will be held on Sept 10 – 11 in Bangalore. The event primarily has two tracks: ESL and DV. The ESL track covers electronic system level (ESL) design and verification, including virtual prototypes of electronic systems and SoCs, pre-silicon software development and debug, power and performance analysis with realistic use cases, architectural exploration, high-level synthesis, and interoperability standards for system models. The DV track coversdesign and verification (DV), including design and verification languages, simulation methodologies based on SystemVerilog, including the Universal Verification Methodology (UVM), and complementary technologies such as formal verification, hardware acceleration, in-circuit emulation (ICE), and prototyping. This year there will be keynotes from Industry veterans, including Harry Foster, Chief Scientist, Design Verification Technology Division, Mentor Graphics; Manoj Gandhi, Executive Vice President and General Manager, Verification Group, Synopsys; and Vinay Shenoy, Managing Director, Infineon Technologies India and Chairman, IESA.

DVCon India is always focused on emerging trends. This year also we will discuss key trends like formal analysis and software driven verification in DV track and virtual platform for verification and performance assessments and high level synthesis in ESL track.

The key topics to be discussed under the ESL track are:

  • Transaction-level modeling of systems and SoC
  • Verification techniques using SystemC-UVM or other C/C++ testbenches
  • High-level synthesis techniques to reduce power and increase performance
  • Hardware-software co-development and co-verification
  • Links between ESL and embedded systems software
  • ESL extensions to handle modeling and verification of analog/mixed-signal (AMS) designs

The key topics to be discussed under the DV trackare:

  • Multi-language and other extensions to the UVM
  • Management of verification process, resources, and metrics
  • Formal techniques, assertion automation/synthesis, and static verification
  • Software-driven verification using C/C++ embedded test cases
  • Debug automation, including identification of error sources
  • DV extensions to handle verification of analog/mixed-signal (AMS) designs

In 2014, the very first DVCon India was held in Bangalore. Two parallel tracks were identified for the conference—“Design and Verification (DV)” and “Electronic System Level (ESL)”—based on the experience gained from the Indian SystemC Group, sponsorship from Accellera and DVCon US. There was an overwhelming response at each stage right from the call for abstracts. Every abstract and tutorial proposal was reviewed by more than three members and finalized for selection after internal discussion. The Technical Program Committee welcomed thoughts from the authors on their papers and made it flexible for them to present in a style that would reach the audience better. Dr. Walden C. Rhines, CEO of Mentor Graphics, Dr. Mahesh Mehendale, CTO, MCU at Texas Instruments, Janick Bergeron, Synopsys Verification Fellow, and Mr. Vishwas Vaidya, AGM, Electronics at Tata Motors, delivered the key speeches. Initial expectations were that a small number of delegates would attend, but DVCon India 2014 managed to bring together over 450 attendees from more than 80 different companies and universities. Feedback from attendees on the two-day event, especially on the technical program, was very encouraging and positive.

We expect the 2015 conference to be a huge success given the strong content and the strenuous efforts put in by the planning team.

You can register for DVCon India 2015 at:

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