Is Interconnect Ready for the Post-mobile SoCs?

The interconnect technology is one of the unsung heroes of the system-on-chip (SoC) revolution. It’s the on-chip networking fabric that is used to link various IP cores on an SoC floorplan. The technology facilitates links between multiple processors, on-chip memories, hardware accelerators and more. In other words, interconnect is the skeleton and nervous system of an SoC device.

As chips get bigger to integrate more functions, they require more IP blocks, which in turn, demonstrates the increasing significance of a robust interconnect technology. Chipmakers have been building the interconnect part of the SoC internally through their internal bus groups; some of them still do that job in-house now. However, the increasing complexity of SoC devices has led to the emergence of specialized players like Arteris, the Campbell, California–based IP supplier who labels the SoC interconnect technology as network-on-chip (NoC).

Arteris calls interconnect the skeleton and nervous system of SoCs

The NoC interconnect technology of Arteris emulates packet transport networking technique for moving information inside an SoC device. Arteris appeared on the chip scene during the mid-2000s when IC vendors began to put the functionality of two to three chips onto a single large chip. Arteris got its first breakthrough when Texas Instruments morphed its interconnect IP into the OMAP4 application processor.

In 2006, Arteris shipped its first interconnect IP product, NoCSolution, which TI licensed for its OMAP SoC in 2007. Both OMPAP 4 and OMAP5 application processors have employed Arteris’ interconnect technology. TI’s OMAP4 chipset powered Motorola’s Droid smartphone while OMAP5 won SoC socket in the Amazon Kindle tablet.

In 2009, Arteris launched its second-generation NoC interconnect IP product—FlexNoC—that featured improved latency and made it easier for chipmakers to use the interconnect technology. Next year, in 2010, SoC powerhouses Qualcomm and Samsung licensed the flexNoC interconnect IP for their mobile chips.

Another high point for Arteris came in 2013 when Samsung used its FlexNoC technology in Exynos 5 Octa chipset which was shipped in the Galaxy 4 smartphones. Most of the world’s smartphones now use Arteris FlexNoC interconnect IP.

Fighting SoC Bottlenecks

The SoC coverage in the trade media is mostly centered on CPUs and GPUs because that’s cool stuff. But it’s crucial to have sophisticated interconnect design that can intelligently address quality-of-service (QoS) requirements for linking different IP building blocks on an SoC. For instance, cameras, CPUs and displays are sensitive about latencies. On the other hand, video codecs are bandwidth hungry.

The interconnect bottlenecks can result into problems such as routing congestion and timing closure. The repercussions of poor interconnect design also include the increase in die size and delay in time-to-market. Third, and probably the most important factor, is the rising cost of SoC designs.

Janac: It’s becoming hard for internal SoC teams to keep up with interconnect challenges

Arteris’ President and CEO Charles Janac points to the fact that the cost of building an interconnect was around $5 million back in the mid-2000s when the SoC movement took off at a larger scale. Now an in-house interconnect job requires an investment of $15 million to $20 million.

Janac adds that interconnect IP allows SoC designers to optimize latencies according to the requirements of the chip, and that can save chipmakers a lot of money. He claims that Arteris’ on-chip networking technology, which uses packetization and serialization techniques, can save SoC makers a couple of square millimeters in die size, 6 to 7 milliwatts of power, and nearly three months in time-to-market.

The interconnect technology is going to have a new set of challenges while SoCs are getting bigger and more power powerful to claim a stake in new market segments. For a start, the aggregate width and length of interconnect links inside an SoC will increase and that can lead to a routing congestion and timing closure déjà vu all over again.

SoC: The Next Frontiers

The specialized interconnect technology had its first major break in consumer-centric devices like mobile phones that began a relentless push for integrating more features at lower costs during the 2000s. The on-chip networking technologies like Arteris FlexNoS also helped mobile chipmakers address the constraints related to die area, power and time-to-market.

Fast forward to 2015 and new challenges are ready for the SoC interconnect fabric. First and foremost, there is a rapidly growing infrastructure for datacenters that will inevitably require more powerful SoC designs. Here, chipmakers are going to add more processor cores to boost energy throughput and thus reduce power consumption of datacenters.

Will interconnect evolve with larger chips and smaller nodes?

A new class of SoC designs will lead to a change in traffic patterns, and that can result in interconnect bottlenecks. Next up, there is the connected car juggernaut, where brand new audio, video and security applications will require a lot more processing horsepower to run intensive software algorithms.

The recent wave of mergers and acquisitions in the semiconductor industry is partly about the rising cost of SoC designs for smaller nodes like 14nm and 10nm. So far, popular SoC designs have ventured into high-volume markets like mobile phones to justify higher costs of complex SoC projects.

Now powerful SoC designs are opening up new avenues in markets such as connected wearables, Internet of Cars and datacenters that demand innovation before high volumes. Here, at this crossroads, interconnect technology, a crucial part of the SoC design, can play a vital role in steering SoCs clear of bottlenecks.

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