A recent comment by a DACattendee mentioned that the IoT acronym was so over-used as to make him get upset at EDA vendors that all purport to be enabling the growing IoT revolution. One of the most common requirements that I hear about IoT electronics is that the power needs to be well understood and controlled during the design exploration phase. Gene Matter at Docea Power is an expert on system level power analysis and modeling, so I’ve followed up with him on this topic.
Q&A
Q: Why is system-level power analysis relevant?
At the recent Cadence Low Power Summit, Nov. 19[SUP]th[/SUP], in San Jose Dr Alon Elad, UC-Berkeley, gave a talk on “Realizing Energy Efficient SoCs Demands Vertically Integrated Design(ers)”. I find myself in agreement with the premise that a Gestalt view of system design can yield a better solution. Specifically, when much of our SoC design has focused on performance, cost, compatibility and features/functions while low power operation is being addressed, energy efficiency may be hindered by the legacy of digital ASIC, CPU-centric design. The re-emergence of sensor-aware networks (motes, smart dust), “Smart” devices (wearable), connected roughly lumped together as the Internet of Things may provide more ideal conditions to look at energy efficient design in a new way.
Dr David Flynn from ARM and Sunrise Micro Devices presented the “Design Challenges in developing Sub-Volt IP Designs for IoT Applications” which gave a useful taxonomy of IoT devices:
- Typically on mature process technology: 180, 90, 65/40 nm: for cost, fabrication, wafer starts/capacity on fully depreciated fabs
- Native power: ICs may operate direct from battery or supply (unregulated) operation which would entail a wide range of voltage operation , low current and duty cycling.
- Mixed signal with multiple sensors: Sensor devices could be fabricated with MEMs + low power analog, altimeter, gyro, accelerometer, magnetic are quite common for position, location. This may also entail multi-die and stacked/heterogenous components vsd. Monolithic silicon
- Near or sub-volt ultra low power connectivity: Mesh and grid-like topology with near field, short range and chirp/small packet payloads, low power wireless such as UWB, BT4, and other low power interfaces.
CORDIO BT4 – Bluetooth Smart IP Component
The devices can be:
- Ultra small, thin, but ruggedized, operating in wide environmental conditions
- Disposable, possible degradable or recoverable
- Un-attended: which requires autonomic/adaptive HW and SW. FW/SW upgrades might be field upgradeable over lossy networks
Q: So what does this have to do with an ESL (electronic system level) approach to power and thermal modeling and simulation?
Docea Power’s approach has been used successfully to model application use cases at the fine grain, instruction, bus and transaction level as well as over long durations such as a “day in the life” scenario.
A good example is the pedestrian detection application with CEA- Letiand STmicroelectronics.
The system designer, can create and analyze scenarios which include a complete network of things (sensor nodes + a mesh network between nodes, an aggregation point and up to a web-based application) with fine grain detail and behavioral or transaction level detail where appropriate.
We have built complex system models with heterogenous devices including mixed signal, analog (PLL, SDDAC, VRs’, sensors), memories and low power digital logic as well as multi-chip, 3D ICs. Here’s the DAC session in 2014 with CEA-LETI.
Q: How is the modeling done in your approach?
By modeling both the electrical behavior with voltage, current, switching activity and task load/task consumption, you get a realistic evaluation of peak, average and transient power data. UsingAceplorer and PTM you can model the adaptive power management efficiency for the types of applications of interest. Building a physical model which is the geometry, material properties, environment, it becomes possible to model power as a function of temperature for different ambient conditions, operational ranges usingThermal profiler.
Q: The IoT appears to be comprised of many different market segments, is that your take too?
While I cannot offer a definitive answer to what is IoT, it is clear that system level optimizations for ultra low power, sub or near threshold logic will create some interesting challenges in the design flow. The smart devices, network of things, has some different critical design parameters in terms of operational life, (1 or 2 or even 5+ years on single battery). Connectivity RF, but not necessarily TCP-IP or internet protocol, but chirpy, short burst activity, not huge packet payloads, always on, but on may just mean sensing activity, accessible and connected. The system architect may need to step away from the legacy installed base of network connectivity, Internet protocol to develop a more compact and efficient networking stack (HW and SW). The power management needs to go beyond race to halt or conventional power management to deal with the wake on event, respond and then nap/slumber nature of IoT nodes.
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