WP_Term Object
(
    [term_id] => 31
    [name] => GlobalFoundries
    [slug] => globalfoundries
    [term_group] => 0
    [term_taxonomy_id] => 31
    [taxonomy] => category
    [description] => 
    [parent] => 158
    [count] => 212
    [filter] => raw
    [cat_ID] => 31
    [category_count] => 212
    [category_description] => 
    [cat_name] => GlobalFoundries
    [category_nicename] => globalfoundries
    [category_parent] => 158
    [is_post] => 1
)

IEDM: TSMC, Intel and IBM 14/16nm Processes

IEDM: TSMC, Intel and IBM 14/16nm Processes
by Paul McLellan on 12-16-2014 at 7:10 am

This week is IEDM. Three of the presentations today were by TSMC, Intel and IBM going over some of the details of their 14/16nm processes. They don’t provide the slides at IEDM, just the single page papers so this may end up being a somewhat random collection of facts.

TSMC were up first. They talked about the improvements that they had made going from their 16FF to the second generation 16FF+ under the title An Enhanced 16nm CMOS Technology Featuring 2nd Generation FinFET Transistors and Advanced Cu/low-k Interconnect for Low Power and High Performance Applications. They already reported on the basic 16FF process last year so this is an update.

The new process core devices are re-optimized to provide additional 15% speed boost or 30% power reduction. Device overdrive capability is also extended by 70mV through reliability enhancement. Superior 128Mb High Density (HD) SRAM Vccmin capability of 450mV is achieved with variability reduction for the first time. Metal capacitance reduction by ~9% is realized with advanced interconnect scheme to enable dynamic power saving.It seems they are using SADP when forming the fins:Fin patterning and formation on bulk silicon with a 48nm fin pitch is realized using pitch-splitting technique where the fin width is determined by the sidewall thickness of a mandrel. Fin profile and gate profile are carefully co-optimized to balanceamong the needs to maintain excellent short channel control, to enhance drive current and to reduce parasitic capacitance of the devices. Poly-silicon deposition and gate patterning with a gate pitch of 90nm on the 3-dimensional fin structure is followed by high-K metal gate (HK/MG) RPG process.

Metal1 pitch is 64nm obtained using an “advanced” patterning scheme (I’m assuming LELE double patterning). Higher levels of metal at 80/90nm pitch are single patterned. There is a 15% speed gain or a 30% power reduction compared to 16FF.

Intel
presented their 14nm Logic Technology Featuring 2nd-Generation FinFET 2 , Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0.0588um[SUP]2[/SUP] SRAM cellsize. They said that their area per transistor shrink was slightly better than the normal shrink (at 49%), and the cost per transistor continues to fall exactly on Moore’s law. The minimum metal pitch is 52nm (only on metal2, metal1 pitch is 70nm and metal0 is 56nm). The fin pitch is 42nm, and the fins are also taller (42nm) and thinner and more square. The contact to gate pitch is 70nm. They have airgaps on just two metal layers, M4 and M6, which products 14-16% performance increase. SADP is used on critical patterning layers. Variation in Vt, which was getting worse with each planar node, improved and 22nm and improves again at 14nm.

They admitted that they have had yield problems, which is public knowledge. 22nm is the highest yielding process in Intel history and 14nm is now almost at the same level. It is shipping in volume.


Using gate pitch multiplied by metal pitch as a proxy for density, Intel have been slightly behind (since TSMC did 28nm when Intel did 32nm, then 20nm when Intel did 22nm, although the timing was such that Intel had earlier production). At 14/16nm this reverses (see diagram).


IBMtalked about their High Performance 14nm SOI FinFET CMOS Technology with 0.0174μm2 embedded DRAM and 15 Levels of Cu Metallization. Of course this is a process that GlobalFoundries will take over when the acquisition of IBM’s semiconductor division is complete.

They have a 42nm fin pitch and 80nm contact/poly (so single pattern and cut mask). Metal1 is 64nm pitch. One interesting feature of the process is that they can created decoupling capacitors on-chip without any additional mask. They can make a 31.5uF decap. With the addition of two masks they can make multi work function. There is a 5X leakage reduction. The 14nm eDRAM unit cell has been scaled down to 0.0174um2, which provides a unique memory solution for cache starved processors.

In the Q&A they were asked if they had SiGe in the fins and refused to comment, which may or may not be significant.

Bottom line: Intel is ahead (by their own reckoning). IBM has the most perfect process for server processors. But I don’t expect to see competitive SoCs out of Intel before TSMC. Competitve microprocessors from IBM sure, although they are not in the merchant market. Competitive microprocessors ahead of TSMC obviously. But SoCs, let’s see how it pans out.

More articles by Paul McLellan…


0 Replies to “IEDM: TSMC, Intel and IBM 14/16nm Processes”

You must register or log in to view/post comments.