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EDA
Posted on by Paul McLellan

Jasper Goes to DVCon

Jasper Goes to DVCon
by Paul McLellan on 02-02-2014 at 6:00 pm
Categories: EDA

As usual, since they are firmly in the verification space, Jasper will have a number of things going on at DVCon 2014 which is March 3-6th at the Doubletree in San Jose. In the exhibition hall they are at booth #402.

Jasper will be happy to talk to you about anything, I’m sure, but the focus this year is on the JasperGold Security Path Verification (SPV) App. This uses formal techniques (no surprise there) to verify that there are no leaks in the hardware. The nice thing about this is that you really want to prove, not just feel fairly certain, that your security is solid and, for example, it is not possible to take over the CPU and send all the encryption keys over the network. I wrote about it recently here. This is the summary paragraph:The Jasper Security Path Verification (SPV) App is used to prove properties about the paths to secured data. For example,

    [*=1]Data in secure area must not be visible by CPU if it is not in secure mode
    [*=1]Secure register must not be written by non-secure agent

Usually data propagation requirements can usually be translated into one of these questions:

    [*=1]Can data on secure location A propagate to non-secure location B?
    [*=1]Can data in non-secure location X propagate to secure location Y?

In both cases we want the answer to be no, but it can be very hard to perform good verification without proper tools. Structural analysis can be very ad-hoc. Simulation depends on how good the verification engineer is at breaking the security. And standard formal verification is not a good fit since it is hard to describe the requirements as SVA/PSL assertions.

Jasper is presenting a SPV App in a tutorial on Thursday March 6th from 8.30am to 12pm in the Carmel room. The tutorial — complete with customer case studies — covers the analysis and verification of the design path leakage that opens a design to hardware hacking. More details on the tutorial Formally Verifying Security Aspects of SoC Designs are here.

Earlier in the week, two JasperGold App users, NVIDIA and Broadcom will be giving presentations. Both presentations are in the Fir ballroom. At 10am NVIDIA will present on chip-wide clock-gating verification. This is followed by Broadcom presenting on detecting x-optimism related bugs. More details on both are here.

Full details on DVCon (including a link to register, sponsored by Jasper yeah) are here.


More articles by Paul McLellan…

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