Date: June 15, 2022 (Wednesday) 13: 15-17: 00
Japan Cadence Design Systems, Inc.
INNOTECH CORPORATION IC Solution Headquarters
Venue: Online (Zoom Webinar)
You can also participate from a web browser.
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Registration deadline: June … Read More
A Digital Event – November 10-11
Ready to share and discuss the latest design and verification best practices with your peers from around the world?
It’s time for our annual JasperTM User Group Conference, held on November 10 and 11 this year. This in-depth technical conference connects designers, verification engineers,… Read More
Simulation dominates hardware functional verification today and likely will continue to dominate for the foreseeable future. Meanwhile formal verification, once thought to be a possible challenger for the title, has instead converged on a more effective role as a complement to simulation. Formal excels at finding problems… Read More
With growing complexities and sizes of SoCs, verification has become a key challenge for design closure. There isn’t a single methodology that can provide complete verification closure for an SoC. Moreover creation of verification environment including hardware, software, testbench and testcases requires significant … Read More
It is the 50th year of IEDM, the International Electron Devices Meeting. The fact that it has been going for so long reveals why it has such an odd name: back in 1964 most “electron devices” were tubes (valves in UK lingo). This year they gave all of us a USB stick with all the papers from all 50 years of the event, something… Read More