SiC Event Banner SemiWiki
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4023
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4023
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
)
EDA
Posted on by Randy Smith

Analysis of HLS Results Made Easier

Analysis of HLS Results Made Easier
by Randy Smith on 07-10-2013 at 4:30 pm
Categories: EDA

In a recent article I discussed how easy it was to debug SystemC source code as shown in a video published on YouTube by Forte Design Systems. I also commented on the usefulness of the well-produced Forte video series. Today, I am reviewing another video in that series on analyzing high-level synthesis (HLS) results.

Cynthesizer Workbench (CynthWB) is much more than a synthesis tool. It is a complete package that gives the user the ability to develop, debug, and analyze SystemC source code. This is in addition to its obvious function of generating RTL from a SystemC description. The workbench gives the user a coherent environment for performing many of the electronic system level (ESL) design tasks.

An important facet of ESL is to compare different possible design implementations in order to decide which style of implementation best meets the constraints for a specific intended use. Sometimes the function may be implemented for maximum speed and another time for lower area. More recently lower power is often the driving constraint. There are simple tables and graphics to show the results as a top level summary. For example, there is a histogram showing the total area of each run with the contributions to each area result from logic, registers, muxes, memory, and control. But much more detail is available.


CynthWB supports side-by-side comparison of the results of two different HLS runs under different conditions making it easy to see how the implementations were impacted by the constraints. The user can view side-by-side views of the parts used, the resulting RTL code, and much more. The video was quite interesting in showing the potential variations in synthesis results.

You can also split the panes in order to cross probe between relevant views of the same run. You can see things such as how a “+” (plus sign) in your SystemC source code maps to a particular adder in the parts list. Using cross probing you can see the relationship between a part in your parts list, where it is used in the RTL, or even where it came from in the original source code. Of course, a particular part may have been generated to implement different lines of source code, like multiple uses of the same adder. This type of bidirectional cross probing is quite useful in determining why certain components are needed which helps you to further optimize your design.


As in the previous Forte video I reviewed, the video is extremely well organized and produced. The total video is less than ten minutes and it is easy to understand the moderator. Of course you cannot learn everything in ten minutes and I imagine there are several advanced features available as well. Still, I recommend viewing the video to get a good idea of the design analysis environment supported by Cynthesizer Workbench. To see what other video are available from Forte click here. I will continue my review of the Forte video series again soon.

lang: en_US

Share this post via:

Comments

There are no comments yet.

You must register or log in to view/post comments.