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NanGate Launches Aggressive DAC Campaign: 50 Library Characterization Licenses for USD 50K

NanGate Launches Aggressive DAC Campaign: 50 Library Characterization Licenses for USD 50K
by Daniel Nenni on 05-30-2013 at 12:00 pm

NanGate today announced a very aggressive “50-50 campaign”. Throughout June and July and in celebration of DAC 50th anniversary, NanGate will be offering 50 licenses of its Library Characterizer™ product for USD 50K for the first year. The offer applies to new customers as well as to existing customers that do not yet license the… Read More


Sagantec’s nmigrate adopted and deployed for 14nm technology

Sagantec’s nmigrate adopted and deployed for 14nm technology
by Daniel Nenni on 05-29-2013 at 3:00 pm

Major semiconductor company successfully migrated 28nm libraries to 14nm FinFET

Santa Clara, California – May 29, 2013 – Sagantec announced that its nmigrate tool was adopted by a major semiconductor company for the development of standard cell libraries at 14nm and 16nm FinFET technologies.
This customer already… Read More


A Brief History of NanGate

A Brief History of NanGate
by Daniel Nenni on 05-23-2013 at 8:10 pm

NanGate got started in 2004 by a group of engineers from Vitesse Semi and Intel. The technology and market idea was to address and solve the inherent shortcomings of standard cell based design as compared to full custom. Anyone having tried to push the performance of a standard cell design knows the frustration… if only I had a betterRead More


Tag it! Your customer will love using IP compliant with TSMC9000 IP Tag specification

Tag it! Your customer will love using IP compliant with TSMC9000 IP Tag specification
by Eric Esteve on 05-16-2013 at 1:26 am

We have seen last week in a first post how crucial was the IP qualification process (TSMC 9000) to increase the probability of successfully Tape Out a chip. Being able to discriminate between dangerous and safe IP is the first step of TSMC 9000 Quality process, IP tagging is the complementary step, almost as essential as the first … Read More


Fabless to OIP

Fabless to OIP
by Paul McLellan on 04-10-2013 at 7:22 pm

Suk Lee drew the short straw at the TSMC Symposium yesterday, with the 5pm slot. Not only late in the day but between all the attendees and free beer. The morning sessions had been standing room only, with several hundred standees (as they call them on muni around here, but isn’t a standee really someone being stood on?). But … Read More


An Analog IC Router

An Analog IC Router
by Daniel Payne on 03-29-2013 at 8:10 pm

Earlier this week I wrote about a Goliath in EDA, Synopsys, and their new analog router, today it’s the David in EDA, Pulsic and their Unity Analog Router. I spoke with several people from Pulsic by phone:

  • Christopher Jost – San Jose
  • Dave Noble – San Jose
  • Fumiaki Sato – Tokyo, Japan
Read More

Schematic Migration Across Foundries and Processes

Schematic Migration Across Foundries and Processes
by Daniel Nenni on 03-17-2013 at 8:10 pm

A dedicated schematic migration tool can save weeks of effort and allow companies to explore new foundry opportunities. Unfortunately moving analog and mixed signal design data between foundries and processes is a complex business. While engineers would rather spend their days creating new circuits, many spend time translating… Read More


Video? Tensilica Has You Covered

Video? Tensilica Has You Covered
by Paul McLellan on 02-12-2013 at 2:01 am

Video is a huge growing area and advanced imaging applications are becoming ubiquitous. By “advanced” I mean more than just things like cameras in your smartphone. There is lots more coming, from high-dynamic range (HDR) photography, gesture recognition, more and more intelligent video in cars to keep us safe, … Read More


Design IP including Multi-standard SerDes enables risk-free, faster customer ASIC designs

Design IP including Multi-standard SerDes enables risk-free, faster customer ASIC designs
by Eric Esteve on 02-01-2013 at 8:25 am

ASIC design service companies are an essential piece of the SC ecosystem, as well as Silicon Foundries, EDA and IP vendors. Their customers range from pure fabless with no ASIC design resources, who need a third party to turn a concept into a real product (IC) and then market and sale it, to large IDM temporarily lacking design resource… Read More


Mobile SoCs: Two Cores are Better Than Four?

Mobile SoCs: Two Cores are Better Than Four?
by Paul McLellan on 01-20-2013 at 8:00 am

I came across an interesting white-paper from ST Ericsson on two topics: multi-processors in mobile platforms and FD-SOI. FD-SOI is the ST Microelectronics alternative to FinFETs for 20nm and below. It stands for Fully-Depeleted Silicon-on-Insulator. But I’m going to save that part of the white-paper for another blog… Read More