WP_Term Object
(
    [term_id] => 14
    [name] => Synopsys
    [slug] => synopsys
    [term_group] => 0
    [term_taxonomy_id] => 14
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 757
    [filter] => raw
    [cat_ID] => 14
    [category_count] => 757
    [category_description] => 
    [cat_name] => Synopsys
    [category_nicename] => synopsys
    [category_parent] => 157
    [is_post] => 
)
            
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WP_Term Object
(
    [term_id] => 14
    [name] => Synopsys
    [slug] => synopsys
    [term_group] => 0
    [term_taxonomy_id] => 14
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 757
    [filter] => raw
    [cat_ID] => 14
    [category_count] => 757
    [category_description] => 
    [cat_name] => Synopsys
    [category_nicename] => synopsys
    [category_parent] => 157
    [is_post] => 
)

Is ARC HS4xD Family More a CPU or DSP IP Core?

Is ARC HS4xD Family More a CPU or DSP IP Core?
by Eric Esteve on 06-02-2017 at 4:00 pm

When I had to define the various IP categories (processor, analog & mixed-signal, wired interfaces, etc.) to build the Design IP Report, I scratched my head for a while about the processor main category: how to define the sub-categories? Not that long ago, it was easy to identify a CPU IP core and a DSP IP core. As of today, if a DSP… Read More


Webinar: Getting to Accurate Power Estimates Earlier and Faster

Webinar: Getting to Accurate Power Estimates Earlier and Faster
by Bernard Murphy on 05-24-2017 at 7:00 am

Power has become a very important metric in modern designs – for mobile and IoT devices which must live on a battery charge for days or years, for datacenters where power costs can be as significant as capital costs, and for increasingly unavoidable regulatory reasons. But accurate power estimation on a design must start from an … Read More


CDC Verification for FPGA – Beyond the Basics

CDC Verification for FPGA – Beyond the Basics
by Bernard Murphy on 05-23-2017 at 12:00 pm

FPGAs have become a lot more capable and a lot more powerful, more closely resembling SoCs than the glue-logic we once considered them to be. Look at any big FPGA – a Xilinx Zynq, an Intel/Altera Arria or a Microsemi SmartFusion; these devices are full-blown SoCs, functionally different from an ASIC SoC only in that some of the device… Read More


Building Better Digital Content Protection

Building Better Digital Content Protection
by Tom Simon on 05-15-2017 at 12:00 pm

Back in college my roommates figured out that the TV cable coax wire was still connected to our apartment. As a result, I was able to watch the Richard Pryor movie Silver Streak about 30 times without a cable box, however the screen was partially jumbled from the simple content protection used back then. This was possible by aggressively… Read More


Polishing Parallelism

Polishing Parallelism
by Bernard Murphy on 05-11-2017 at 7:00 am

The great thing about competition in free markets is that vendors are always pushing their products to find an edge. You the consumer don’t have to do much to take advantage of these advances (other than possibly paying for new options). You just sit back and watch the tool you use get faster and deliver better QoR. You may think that… Read More


Data Center Explosion Push for Fast Adoption of 25G

Data Center Explosion Push for Fast Adoption of 25G
by Eric Esteve on 05-04-2017 at 12:00 pm

The data center rack server market is estimated to growat a high Compound Annual Growth Rate (CAGR) of 20% to reach $90 billion by 2021. Such growth is due to the significantly rise in the number of connected devices, the growth in the volume of data per device and theneed for quick processing of high-volume data. Much of these data … Read More


Quantifying Formal Coverage

Quantifying Formal Coverage
by Bernard Murphy on 05-03-2017 at 7:00 am

Verification coverage is a tricky concept. Ideally a definition would measure against how many paths were tested of every possible path through the complete state graph, but that goal is unimaginably out of reach for any typical design. Instead we fall back on proxies for completeness, like hitting every line in the code. This … Read More


EDA CEO Outlook 2017

EDA CEO Outlook 2017
by Daniel Nenni on 04-28-2017 at 7:00 am

A long standing tradition has returned to EDA: The CEO Outlook sponsored by ESDA (formerly EDAC) which alone is worth the price of membership! Not only do you get a free meal, the event included quality networking time with the semiconductor elite. In the past, financial analysts moderated this event holding the CEO’s feet to the… Read More


Webinar: Getting to Formal Coverage

Webinar: Getting to Formal Coverage
by Bernard Murphy on 04-20-2017 at 10:00 am

Facing rapidly growing challenges in getting to respectable coverage, designers have been turning more and more to formal verification, not just to plug gaps but increasingly to take over verification of significant components of the testplan. Which is great, but at the end of the day any approach to verification must be measured… Read More


When Will we Replace the 3.5 mm Jack in Modern Phones?

When Will we Replace the 3.5 mm Jack in Modern Phones?
by Eric Esteve on 04-05-2017 at 7:00 am

You have certainly experienced that modern mobile phones are used for more than phone calls and do not have room for multiple connectors. A new approach for audio connectivity is needed, allowing product designers to retire the 3.5mm jack. Considering the USB audio protocol to replace the analog audio solutions, typically using… Read More