CAST Compression IP Webinar 800x100 (2)
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ESL Expertise when You Need It. Spinning Up Faster

ESL Expertise when You Need It. Spinning Up Faster
by Bernard Murphy on 12-30-2020 at 6:00 am

CircuitSutra min

System-level expertise, once the domain a few architecture specialists, is now shouldering its way everywhere into chip design and verification. In virtual modeling together with OS and application software certainly. That now couples into mixed-level system-verification, using different levels of abstraction for different… Read More


NetApp’s FlexGroup Volumes – A Game Changer for EDA Workflows

NetApp’s FlexGroup Volumes – A Game Changer for EDA Workflows
by Mike Gianfagna on 12-23-2020 at 10:00 am

NetApps FlexGroup Volumes – A Game Changer for EDA Workflows

In my prior post on NetApp, I discussed how the company’s FlexCache technology can keep distributed design teams in sync. Coordination and collaboration are critical elements of any complex design project. The ability to deliver results quickly while managing the massive amounts of data is also a critical element of success.… Read More


SMIC Blacklist puts ASML in Jam

SMIC Blacklist puts ASML in Jam
by Robert Maire on 12-20-2020 at 6:00 am

SMIC Blacklisted US

US BIS confirms our prediction of “blacklisting” SMIC
SMIC embargoed from 10NM or better technology
Likely related to ASML pressure & WH scorched earth

Not just the stock

We had received a lot of feedback on our Nov 30th note regarding blacklisting of SMIC suggesting that we were wrong and the only thing blacklisted… Read More


Silicon Catalyst’s Semi Industry Forum – All-Star Cast Didn’t Disappoint

Silicon Catalyst’s Semi Industry Forum – All-Star Cast Didn’t Disappoint
by Mike Gianfagna on 12-18-2020 at 10:00 am

Silicon Catalysts Semi Industry Forum – All Star Cast Didnt Disappoint

A few weeks ago I wrote about an upcoming event Silicon Catalyst was hosting, the Semiconductor Industry Forum – A View to the Future. I mentioned a high-profile group of presenters: Don Clark, Contributing Journalist, New York Times as moderator;  Mark Edelstone, Chairman of Global Semiconductor Investment Banking, Morgan… Read More


An Accellera Update. COVID Accelerates Progress

An Accellera Update. COVID Accelerates Progress
by Bernard Murphy on 12-17-2020 at 6:00 am

logo accellera min

Normally I would post this Accellera update during DVCon US but, no surprise, this year is weird. Particularly in conferences going virtual. The last DVCon was in early March of this year, right on the cusp of the shutdown. I was there in person, as was Lu Dai (Chairman of Accellera). Both Synopsys and Cadence had dropped out, citing… Read More


5 Things You Need to Plan for System Custom Silicon

5 Things You Need to Plan for System Custom Silicon
by Raul Perez on 12-13-2020 at 10:00 am

logo4semiwiki

I used to be part of the custom silicon management team at Apple.  I’ve seen how great a challenge it is to pull off a custom silicon strategy within a one year product cycle. Apple is the perfect example of this custom silicon model since they develop the best mobile processors in the world for their products. Which also includes otherRead More


Chip Startups are Succeeding with Silicon Catalyst and Partners Like Arm

Chip Startups are Succeeding with Silicon Catalyst and Partners Like Arm
by Mike Gianfagna on 12-04-2020 at 6:00 am

Chip Start Ups are Succeeding with Silicon Catalyst and Partners Like Arm

Earlier this year I wrote about Silicon Catalyst and a potent new addition to their In-Kind and Strategic Partner Programs, Arm. Fast-forward to today and there are real results to report.  As I mentioned in the prior post, Silicon Catalyst provides a unique incubator environment which includes deeply discounted technology … Read More


Sign Off Design Challenges at Cutting Edge Technologies

Sign Off Design Challenges at Cutting Edge Technologies
by Tom Simon on 12-03-2020 at 6:00 am

Power and Ground Design Challenges

As semiconductor designs for many popular products move into smaller process nodes, the need for effective and rapid design closure is increasing. The SOCs used for many consumer and industrial applications are moving to FinFET nodes from 16 to 7nm and with that comes greater challenges in obtaining design closure. einfochips,… Read More


No Intel and Samsung are not passing TSMC

No Intel and Samsung are not passing TSMC
by Scotten Jones on 12-02-2020 at 6:00 am

Slide1

Seeking Alpha just published an article about Intel and Samsung passing TSMC for process leadership. The Intel part seems to be a theme with them, they have talked in the past about how Intel does bigger density improvements with each generation than the foundries but forget that the foundries are doing 5 nodes in the time it takes… Read More


Noose tightens on SMIC- Dead Fab Walking?

Noose tightens on SMIC- Dead Fab Walking?
by Robert Maire on 12-01-2020 at 6:00 am

SMIC US Embargo

-US Administration to “blacklist” SMIC- Cutting off ALL US help
-A slow death versus a quick death (unlike Jinhua)
-There is enough time on way out door to leave scorched earth
-Reports in the Media about SMIC being “Blacklisted”

It has been widely reported that SMIC will be added to the US “Blacklist”… Read More