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Things From Intel 10K That Make You Go …. Hmmmm

Things From Intel 10K That Make You Go …. Hmmmm
by Admin on 03-08-2026 at 8:00 am

MKW Ventures Semiconductors

INTEL FORM 10-K

☑ ANNUAL REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934
For the fiscal year ended December 27, 2025.

1) Intel is constrained on manufacturing. Not by TSMC. But by IFS and mainly by Intel 7, a node from 2021. Normally constraints are good, it means you are running efficiently with lots of … Read More


Podcast EP333: A Look at the Broad, Worldwide Impact SEMI Has on the Semiconductor Industry with Ajit Manocha

Podcast EP333: A Look at the Broad, Worldwide Impact SEMI Has on the Semiconductor Industry with Ajit Manocha
by Daniel Nenni on 02-27-2026 at 10:00 am

Daniel is joined by Ajit Manocha, president and CEO of SEMI, the global industry association serving the semiconductor and electronics manufacturing and design supply chain. Throughout his career, Manocha has been a champion of industry collaboration as a critical means of advancing technology for societal and economic prosperity.… Read More


AI Drives Strong Semiconductor Market in 2025-2026

AI Drives Strong Semiconductor Market in 2025-2026
by Bill Jewell on 02-26-2026 at 1:00 pm

2026 Market Forecast

The global semiconductor market in 2025 was $792 billion, according to WSTS. 2025 was up 25.6% from 2024, the strongest growth since 26.2% in the COVID recovery year 2021. The increase was driven by AI, with Nvidia revenues up 65%. The major memory companies (Samsung, SK Hynix, Micron Technology, Kioxia and Sandisk) all cited AI… Read More


Akeana Partners with Axiomise for Formal Verification of Its Super-Scalar RISC-V Cores

Akeana Partners with Axiomise for Formal Verification of Its Super-Scalar RISC-V Cores
by Daniel Nenni on 02-26-2026 at 8:00 am

Akeana Partners with Axiomise

Akeana Inc. announced a key milestone in the development of its advanced RISC-V technology: a successful partnership with Axiomise Limited to formally verify its super-scalar test chip, Alpine. The collaboration highlights the growing importance of formal verification in ensuring correctness, performance, and efficiency

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Agentic EDA Panel Review Suggests Promise and Near-Term Guidance

Agentic EDA Panel Review Suggests Promise and Near-Term Guidance
by Bernard Murphy on 02-24-2026 at 6:00 am

Massive AI datacenter

NetApp recently hosted a webinar on Agentic AI as the future for EDA and implications for infrastructure. Good list of panelists including Mahesh Turaga (VP Cadence Cloud) with an intro preso on infrastructure and agentic AI at Cadence, then our own Dan Nenni (Mr. SemiWiki) moderating, Khaled Heloue (Fellow AMD, CAD CAD/Methodology/AI),… Read More


The Name Changes but the Vision Remains the Same – ESD Alliance Through the Years

The Name Changes but the Vision Remains the Same – ESD Alliance Through the Years
by Mike Gianfagna on 02-23-2026 at 6:00 am

The Name Changes but the Vision Remains the Same – ESD Alliance Through the Years

The Electronic System Design Alliance (ESDA) has been at the center of the EDA industry through its many changes over the years. It occurred to me that an update on this organization would be useful. ESDA is a technology community within SEMI and is managed primarily by a team of three who coordinate all its activities along with a … Read More


Samtec Ushers in a New Era of High-Speed Connectivity at DesignCon 2026

Samtec Ushers in a New Era of High-Speed Connectivity at DesignCon 2026
by Mike Gianfagna on 02-16-2026 at 10:00 am

Samtec Ushers in a New Era of High Speed Connectivity at DesignCon 2026

As I’ve discussed before, Samtec has a way of dominating every trade show the company participates in. The upcoming DesignCon event is no exception. At the show, Samtec will be discussing data rates up to 448 Gbps and signals up to 130 GHz. Beyond a rich set of demonstrations in the company’s booth, Samtec engineers will be participating… Read More


Silicon Catalyst at the Chiplet Summit: Advancing the Chiplet Economy

Silicon Catalyst at the Chiplet Summit: Advancing the Chiplet Economy
by Daniel Nenni on 02-12-2026 at 10:00 am

Chiplet Summit 2026

The rapid evolution of semiconductor design has elevated chiplets from a niche concept to a foundational strategy for next-generation computing. At the upcoming Chiplet Summit – February 17–19, 2026 Santa Clara Convention Center. Silicon Catalyst will play a central role in shaping this conversation, highlighting… Read More


Accellera Strengthens Industry Collaboration and Standards Leadership at DVCon U.S. 2026

Accellera Strengthens Industry Collaboration and Standards Leadership at DVCon U.S. 2026
by Daniel Nenni on 02-10-2026 at 10:00 am

DVCON 2026

At DVCon U.S. 2026, Accellera Systems Initiative reinforces its central role in shaping the future of electronic design and verification through a focused program of workshops, tutorials, and community engagement. As system complexity continues to rise across AI, automotive, HPC, and communications markets, the need for… Read More


Podcast EP330: An Overview of DVCon U.S. 2026 with Xiaolin Chen

Podcast EP330: An Overview of DVCon U.S. 2026 with Xiaolin Chen
by Daniel Nenni on 02-06-2026 at 10:00 am

Daniel is joined by Xiaolin Chen, Senior Director of Technical Product Management for Formal Solutions at Synopsys. She has over 20 years of experience applying formal technology in verification and partnering with customers to identify opportunities where formal methods are best suited to solve complex verification challenges.… Read More