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Formal For All!
“Do I need a PhD to use formal verification?”
“Can formal methods really scale?”
“Is it too difficult to write formal properties that actually prove something?”
“If I can’t get a proof, should I just hope for the best?”
“Do formal methods even offer useful coverage metrics?”
Discouraging words to say the least, but… Read More
The 2024 DVCon (Design and Verification) Europe conference took place on October 15 and 16, in its traditional location at the Holiday Inn Munich City Centre. Artificial intelligence and software were prominent topics, along with the traditional DVCon topics like virtual platforms, RTL verification, and validation.
KLA reported… Read More
It coulda been… Read More
AI (artificial intelligence) is widely cited as a growth driver for the technology industry, including semiconductors. While AI is in its early stages, opinions vary on whether it will become common in the next few years. A McKinsey study from May 2024 showed 72% of organizations have adopted AI in at least one business function.… Read More
2.5D package design is rapidly finding its stride in a wide variety of applications, including AI. While there are still many challenges to its widespread adoption, the chiplet approach is becoming more popular compared to monolithic design. However, the required market to create a chiplet ecosystem is still under development.… Read More
The ASIC business has always been a key enabler of the semiconductor industry but it is a difficult business. In my 40 years I have seen many ASIC companies come and go but I have never seen one like Alchip.
Alchip Technologies Ltd. was founded more than 20 years ago, about half way through my career. I know one of the founders, a fiercely… Read More
Many of you are already familiar with Silicon Catalyst and the value it brings to semiconductor startups, the industry and the electronics industry at large. Silicon Catalyst is an organization that supports early-stage semiconductor startups with an ecosystem that provides tools and resources needed to design, create, and… Read More
– SPIE Photomask -all about High NA and bigger masks
– High NA will ramp very fast & is ramping fast – two already at Intel
– Doubling size of photomask will offset High NA exposure size problem
– Assembling litho tools at customer saves time/money- “Scanner Kits”
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