WP_Term Object
(
    [term_id] => 24
    [name] => TSMC
    [slug] => tsmc
    [term_group] => 0
    [term_taxonomy_id] => 24
    [taxonomy] => category
    [description] => 
    [parent] => 158
    [count] => 498
    [filter] => raw
    [cat_ID] => 24
    [category_count] => 498
    [category_description] => 
    [cat_name] => TSMC
    [category_nicename] => tsmc
    [category_parent] => 158
    [is_post] => 
)
            
TSMC Banner SemiWiki
WP_Term Object
(
    [term_id] => 24
    [name] => TSMC
    [slug] => tsmc
    [term_group] => 0
    [term_taxonomy_id] => 24
    [taxonomy] => category
    [description] => 
    [parent] => 158
    [count] => 498
    [filter] => raw
    [cat_ID] => 24
    [category_count] => 498
    [category_description] => 
    [cat_name] => TSMC
    [category_nicename] => tsmc
    [category_parent] => 158
    [is_post] => 
)

Apple A14 Die Annotation and Analysis – Terrifying Implications For The Industry

Apple A14 Die Annotation and Analysis – Terrifying Implications For The Industry
by Dylan Patel on 12-20-2020 at 10:00 am

Apple A14 Die Analysis

SemiAnalysis and SkyJuice have teamed up in order to analyze the A14 die shot from ICmasters. Our previous analysis of the A14, delved into why Apple and TSMC have deviated from previous generations when comparing theoretical logic transistor density to a real world utilized transistor density.

Read More

Advanced Process Development is Much More than just Litho

Advanced Process Development is Much More than just Litho
by Tom Dillinger on 12-16-2020 at 10:00 am

Vt distribution

The vast majority of the attention given to the introduction of each new advanced process node focuses on lithographic updates.  The common metrics quoted are the transistors per mm**2 or the (high-density) SRAM bit cell area.  Alternatively, detailed decomposition analysis may be applied using transmission electron microscopy… Read More


Design Considerations for 3DICs

Design Considerations for 3DICs
by Tom Dillinger on 12-14-2020 at 6:00 am

LVS flow phases

The introduction of heterogeneous 3DIC packaging technology offers the opportunity for significant increases in circuit density and performance, with corresponding reductions in package footprint.  Yet, the implementation of a complex 3DIC product requires a considerable investment in methodology development for all… Read More


Apple’s A14 Packs 134 Million Transistors/mm², but Falls Short of TSMC’s Density Claims

Apple’s A14 Packs 134 Million Transistors/mm², but Falls Short of TSMC’s Density Claims
by Dylan Patel on 12-11-2020 at 6:00 am

Apple 14 TSMC 5nm Transister Packing 1

Our friends over at ICmasters have delved into the package of the Apple A14 Bionic. The die size has been unmasked, and it stands in at 88mm2. Despite cramming in 11.8 billion transistors, the die size is incredibly small thanks to utilization of TSMC’s 5nm process node.

The march of progress is not all rosy. Apple’s chips have historically… Read More


How Intel Stumbled: A Perspective from the Trenches

How Intel Stumbled: A Perspective from the Trenches
by Daniel Nenni on 12-07-2020 at 6:00 am

Stacy and Bob Intel SemiWiki

Bloomberg did an interview with my favorite semiconductor analyst Stacy Rasgon on “How the Number One U.S. Semiconductor Company Stumbled” that I found interesting. Coupled with the Q&A Bob Swan did at the Credit Suisse Annual Technology Conference I thought it would be good content for a viral blog.

Stacy RasgonRead More


No Intel and Samsung are not passing TSMC

No Intel and Samsung are not passing TSMC
by Scotten Jones on 12-02-2020 at 6:00 am

Slide1

Seeking Alpha just published an article about Intel and Samsung passing TSMC for process leadership. The Intel part seems to be a theme with them, they have talked in the past about how Intel does bigger density improvements with each generation than the foundries but forget that the foundries are doing 5 nodes in the time it takes… Read More


Can Samsung Foundry Really Compete with TSMC?

Can Samsung Foundry Really Compete with TSMC?
by Daniel Nenni on 11-20-2020 at 6:00 am

Samsung TSMC 3nm Battle SemiWiki

The semiconductor foundry business has been front page news of late and for good reason, it’s an exciting time in the semiconductor industry and the foundries are where it all begins. Unfortunately, most of the “exciting” news has been overblown but this topic is of great interest, to me at least. Having been intimately involved… Read More


TSMC to Build first US Fab in Arizona!

TSMC to Build first US Fab in Arizona!
by Daniel Nenni on 11-15-2020 at 10:00 am

TSMC North America SemiWiki

Well, it’s official, the TSMC Board of Directors approved an investment to establish a wholly-owned subsidiary in Arizona with a paid-in capital of $3.5 billion. As history shows the investment may be more than that but $3.5B is a great starting point. This is being discussed in the SemiWiki Forum  and I have been gathering inside… Read More


Are TSMC and Intel Partnering in Arizona?

Are TSMC and Intel Partnering in Arizona?
by Daniel Nenni on 11-01-2020 at 10:00 am

TSMC Career Opporunitites

After months of back and forth TSMC finally announced plans to build a fab in Arizona. The announcement was not made in the press or on the most recent investor call but on LinkedIn. A sign of the times I guess but since they need to hire a bunch of semiconductor people it was more than appropriate.

“We’re delighted to catch up with you … Read More


Intel TSMC Update!

Intel TSMC Update!
by Daniel Nenni on 10-23-2020 at 10:00 am

Intel Bob Swan TSMC SemiWiki 1

Based on the Intel investor call yesterday here are some interesting comments Bob Swan made related to Intel outsourcing manufacturing and 7nm progress. Let’s start with the prepared statement:

Bob Swan: Over the last couple of years, we have been focused on three critical priorities; improving our execution to strengthen … Read More