Banner Electrical Verification The invisible bottleneck in IC design updated 1
WP_Term Object
(
    [term_id] => 178
    [name] => IP
    [slug] => ip
    [term_group] => 0
    [term_taxonomy_id] => 178
    [taxonomy] => category
    [description] => Semiconductor Intellectual Property
    [parent] => 0
    [count] => 1925
    [filter] => raw
    [cat_ID] => 178
    [category_count] => 1925
    [category_description] => Semiconductor Intellectual Property
    [cat_name] => IP
    [category_nicename] => ip
    [category_parent] => 0
    [is_post] => 
)

CEO Interview: Tony Pialis of Alphawave IP

CEO Interview: Tony Pialis of Alphawave IP
by Daniel Nenni on 12-04-2020 at 10:00 am

Tony Pialis Alphawave on SemiWiki

Tony Pialis is a visionary entrepreneur focused on developing
technologies for next generation connectivity. In the last twenty 20 years, he has co-founded three semiconductor IP companies, all exclusively targeting connectivity IP. Tony is currently the CEO of Alphawave IP Inc, a leader in delivering multi-standard wireline… Read More


Analog Bits is Supplying Analog Foundation IP on the Industry’s Most Advanced FinFET Processes

Analog Bits is Supplying Analog Foundation IP on the Industry’s Most Advanced FinFET Processes
by Mike Gianfagna on 12-02-2020 at 10:00 am

Analog Bits is Supplying Analog Foundation IP on the Industrys Most Advanced FinFET Processes

The industry recently concluded a series of technology events for the all the major foundries.  Done as virtual events this year, each one provided a significant update on technology platforms, roadmaps and ecosystem partnerships. These events are quite valuable to chip design teams who need to be aware of the latest in process,… Read More


PLDA Brings Flexible Support for Compute Express Link (CXL) to SoC and FPGA Designers

PLDA Brings Flexible Support for Compute Express Link (CXL) to SoC and FPGA Designers
by Mike Gianfagna on 11-30-2020 at 10:00 am

PLDA Brings Flexible Support for Compute Express Link CXL to SoC and FPGA Designers

A few months ago, I posted a piece about PLDA expanding its support for two emerging protocol standards: CXL™ and Gen-Z™.  The Compute Express Link (CXL) specification defines a set of three protocols that run on top of the PCIe PHY layer. The current revision of the CXL (2.0) specification runs with the PCIe 5.0 PHY layer at a maximum… Read More


Low Power SRAM Register Files for IoT, AI and Wearables

Low Power SRAM Register Files for IoT, AI and Wearables
by Tom Simon on 11-26-2020 at 10:00 am

SRAM register files

SRAM is the workhorse for on-chip memories, valued for its performance and easy integration with standard processes. The needs of wearable, IoT and AI SOCs have put a lot of pressure on the requirements for all on-chip memories. This is perhaps most evident in the area of power. AI chips that rely heavily on SRAM register files are… Read More


Folding at Home. The Ultimate in Parallel Acceleration

Folding at Home. The Ultimate in Parallel Acceleration
by Bernard Murphy on 11-26-2020 at 6:00 am

COVID spike protein min

You may have heard of Folding at Home. It’s a very creative way that a bioengineering team, based at Washington University in St Louis, are modeling the process of protein folding. Greg Bowman, an associate professor of biochemistry and biophysics at the university directs the project and presented at Arm DevSummit this year. … Read More


Webinar Replay on TileLink from Truechip

Webinar Replay on TileLink from Truechip
by Tom Simon on 11-24-2020 at 10:00 am

TileLink

The extremely popular RISC-V instruction set architecture (ISA) originally came from the Berkeley Architecture Research (BAR) group. BAR also developed several other key pieces of enabling technology that have helped RISC-V become so popular. Among these are Rocket Chip which serves as a RISC-V based SOC generator. It can … Read More


The Reality of ISO 26262 Interpretation. Experience Matters

The Reality of ISO 26262 Interpretation. Experience Matters
by Bernard Murphy on 11-24-2020 at 6:00 am

Man scratching head min

Interpreting ISO 26262 without ambiguity is not always easy. Suppliers and integrators can read some aspects differently, creating confusion. Which is a problem since ISO 26262 has become so much a part of any discussion on automotive electronics that it has gained almost biblical significance. Yet most of us, even suppliers… Read More


Better Speech Recognition by Reducing Babble

Better Speech Recognition by Reducing Babble
by Bernard Murphy on 11-17-2020 at 6:00 am

I’ve become a bit of a connoisseur of voice-based control, so when Chris Rowen did a pitch on Babble Labs at Arm Dev Summit last month, I wanted to listen in.  Chris was the CEO of Babble Labs, recently acquired by the Cisco Webex group where he’s now listed as VP Engineering of the Voice Technology Group. You should expect to see this… Read More


Powering the Next Generation of Hearables and Wearables with Chipus

Powering the Next Generation of Hearables and Wearables with Chipus
by Mike Gianfagna on 11-16-2020 at 10:00 am

Powering the Next Generation of Hearables and Wearables with Chipus

Chipus is an interesting company. It’s been around since 2008 and focuses on mixed-signal ASICs, intellectual property blocks and IC design services. They are headquartered on the island of Florianopolis, which is described as the most dense startup ecosystem in Brazil. The company has substantial skills in analog and mixed… Read More


Agile and DevOps for Hardware. Keynotes at DVCon Europe

Agile and DevOps for Hardware. Keynotes at DVCon Europe
by Bernard Murphy on 11-12-2020 at 6:00 am

Agile and DevOps for Hardware

Paul Cunningham (Verification CVP/GM at Cadence) initiated our monthly Innovation in Verification blog to hunt for novel ideas in verification, breaking past the usual steady, necessary but undramatic pace of incremental advances. I attended a couple of sessions from DVCon Europe recently, and was encouraged to hear a couple… Read More