Intel recently made headlines when CEO Pat Gelsinger unveiled the world’s first UCIe interoperability test chip demo at Innovation 2023. The test chip built using advanced packaging technology is codenamed Pike Creek and is used to demonstrate interoperability across chiplets designed by Intel and Synopsys. More details … Read More
Semiconductor Intellectual Property
Podcast EP197: A Tour of the RISC-V Movement and SiFive’s Contributions with Jack Kang
Dan is joined by Jack Kang of SiFive. As a member of the founding team at SiFive, Jack oversees the Business Development, Customer Experience, and Corporate Marketing groups. He is responsible for strategic business initiatives and partnerships, technical pre-sales activities and post-sales support, and corporate messaging… Read More
CEO Interview: Suresh Sugumar of Mastiska AI
Suresh is a technology executive with deep technical expertise in semiconductors, artificial intelligence, cybersecurity, internet-of-things, hardware, software, etc. He spent 20 years in the industry, most recently serving as an Executive Director for open-source zero-trust chip development at Technology Innovation… Read More
5G Aim at LEO Satellites Will Stimulate Growth and Competition
Low earth orbit (LEO) satellites as an intermediary for communication became hot when Elon Musk announced Starlink (yeah, other options were available, but Elon Musk). This capability extends internet availability to remote areas and notably (for a while) to Ukraine in support of the war with Russia. Satellites can in principle… Read More
RISC-V Summit Buzz – Semidynamics Founder and CEO Roger Espasa Introduces Extreme Customization
Founded in 2016 and based in Barcelona, Spain, Semidynamics™ is the only provider of fully customizable RISC-V processor IP. The company delivers high bandwidth, high performance cores with vector units and tensor units targeted at machine learning and AI applications. There were some recent announcements from Semidynamics… Read More
Synopsys 224G SerDes IP’s Extensive Ecosystem Interoperability
Hyperscale data centers are evolving rapidly to meet the demands of high-bandwidth, low-latency applications, ranging from AI and high-performance computing (HPC) to telecommunications and 4K video streaming. The increasing need for faster data transfer rates has prompted a scaling of Ethernet from 51Tb/s to 100Tb/s. Numerous… Read More
Navigating Edge AI Architectures: Power Efficiency, Performance, and Future-Proofing
The surge in Edge AI applications has propelled the need for architectures that balance performance, power efficiency, and flexibility. Architectural choices play a pivotal role in determining the success of AI processing at the edge, with trade-offs often necessary to meet the unique demands of diverse workloads. There are… Read More
Podcast EP194: The Impact of Joining TSMC’s OIP From the Perspective of Agile Analog
Dan is joined by Chris Morrison. Chris has 15 years’ experience of delivering innovative analog, digital, power management and audio solutions for international electronics. Currently he is the director of product marketing at Agile Analog, the analog IP innovators. Previously he has held engineering positions, including… Read More
RISC-V Summit Buzz – Ron Black Unveils Codasip’s Paradigm Shift for Secured Innovation
Codasip is a processor solutions company with an expanding footprint. It is Europe’s leading RISC-V organization with a global presence. Codasip reports billions of chips already use its technology. You can learn more about Codasip here, The company has made some announcements recently that expand its offerings in terms … Read More
NoCs give architects flexibility in system-in RISC-V design
RISC-V tends to generate excitement over the possibilities for the processor core, any custom instruction extensions, and its attached memory subsystem. Those are all necessary steps to obtaining system-level performance. But is that attention sufficient? Architects who have ventured into larger system-on-chip (SoC) … Read More


Disaggregating AI Compute to Break the Tokens Barrier