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IP

Semiconductor Intellectual Property

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Arteris FlexNoC penetration increase… everywhere

Arteris FlexNoC penetration increase… everywhere
by Eric Esteve on 08-02-2012 at 9:00 pm
Categories: Arm, Arteris, IP

The need for Network-on-Chip (NoC) has appeared at the time where chip makers realized that they could really integrate a complete system on a single die to build a System-on-Chip (SoC). At the early times (1995-2005), the so-call NoC IP suppliers were in fact proposing a crossbar switch, a pretty old concept initially developed… Read More

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The Coming Battle for AMD’s x86 Hidden Cache

The Coming Battle for AMD’s x86 Hidden Cache
by Ed McKernan on 07-30-2012 at 10:58 am
Categories: Arm, Foundries, Intel

Not yet a year into Rory Read’s term and the AMD board must be considering that the value of the x86 patents and engineering talent is worth much more than the stocks $3B valuation and easier to fathom putting on the auction block than continuing to sell $25 processors into the back channels of China and the Developing World. As I read… Read More

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ARM and TSMC Beat Revenue Expectations Signaling Strength in a Weakening Economy?

ARM and TSMC Beat Revenue Expectations Signaling Strength in a Weakening Economy?
by Daniel Nenni on 07-25-2012 at 11:00 am
Categories: Arm, Foundries, IP, TSMC

Fabless semiconductor ecosystem bellwethers, TSMC and ARM, buck the trend reporting solid second quarters. Following “TSMC Reports Second Highest Quarterly Profit“, the British ARM Holdings “Outperforms Industry to Beat Forecasts“. Clearly the tabloid press death of the fabless ecosystem claims… Read More

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Shorter, better and easier PCIe and NVM Express Verification flow with advanced technologies

Shorter, better and easier PCIe and NVM Express Verification flow with advanced technologies
by Eric Esteve on 07-19-2012 at 8:05 pm
Categories: Cadence, IP

We have talked about Cadence subsystem IP strategy, illustrated by NVM Express subsystem IP, in a previous blog. What we said was that “A subsystem IP based approach will also speed up the software development and validation phase: if the IP provider is able to propose the right tools, like the associated Verification IP (VIP), … Read More

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CEVA-XC4000 new DSP IP core

CEVA-XC4000 new DSP IP core
by Eric Esteve on 07-19-2012 at 9:53 am
Categories: Ceva, IP

The CEVA-XC4000 offers unparalleled, scalable performance capabilities and innovative power management to address the most demanding communication standards, including LTE-Advanced, 802.11ac and DVB-T2, on a single architecture. Building upon its highly successful predecessors, the CEVA-XC4000 architecture sets… Read More

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It Takes a Village: Mentor and ARM Team Up on Test

It Takes a Village: Mentor and ARM Team Up on Test
by Beth Martin on 07-18-2012 at 5:01 pm
Categories: Arm, EDA, IP, Siemens EDA

Benjamin Franklin, “I didn’t fail the test, I just found 100 ways to do it wrong.” I was reminded of this line during a joint Mentor-ARM seminar yesterday about testing ARM cores and memories. The complexity of testing modern SoC designs at advanced nodes, with multiple integrated ARM cores and other IP, opens up plenty of room for… Read More

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Testing ARM Cores – Mentor and ARM Lunch Seminar

Testing ARM Cores – Mentor and ARM Lunch Seminar
by Beth Martin on 07-08-2012 at 8:29 pm
Categories: Arm, EDA, IP, Siemens EDA

If you are involved in testing memory or logic of ARM-based designs, you’ll want to attend this free seminar on July 17, 2012 in Santa Clara. Mentor Graphics and ARM have a long standing partnership, and have optimized the Mentor test products (a.k.a Tessent) for the ARM processors and memory IP.

The lunch seminar runs from 10:30-1:00… Read More

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Mind the Gap — Overcoming the processor-memory performance gap to unlock SoC performance

Mind the Gap — Overcoming the processor-memory performance gap to unlock SoC performance
by Sundar Iyer on 07-06-2012 at 3:25 pm
Categories: IP

Remember the processor-memory gap— a situation where the processor is forced to stall while waiting for a memory operation to complete? This was largely a result of the high latency required for off chip memory accesses. Haven’t we solved that problem now with SoCs? SoCs are typically architected with their processors … Read More

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IC Design at Novocell Semiconductor

IC Design at Novocell Semiconductor
by Daniel Payne on 07-05-2012 at 12:09 pm
Categories: EDA, IP, Tanner EDA
5 Comments

In my circuit design past I did DRAM work at Intel, so I was interested in learning more about Novocell Semiconductor and their design of One Time Programmable (OTP) IP. Walter Novosell is the President/CTO of Novocell and talked with me by phone on Thursday.… Read More

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Cadence’s NVM Express: fruit from subsystem IP based strategy

Cadence’s NVM Express: fruit from subsystem IP based strategy
by Eric Esteve on 07-02-2012 at 11:24 am
Categories: Cadence, IP

If we look at SoC design evolution, we have certainly successfully passed several steps: from transistor by transistor IC design using Calma up to design methodology based on the integration of 500K + gates IP like PCIe gen-3 Controller, one out of several dozens of IP integrated in today’ SoC for Set-Top-Box or Wireless Application… Read More