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WP_Term Object
(
    [term_id] => 178
    [name] => IP
    [slug] => ip
    [term_group] => 0
    [term_taxonomy_id] => 178
    [taxonomy] => category
    [description] => Semiconductor Intellectual Property
    [parent] => 0
    [count] => 1916
    [filter] => raw
    [cat_ID] => 178
    [category_count] => 1916
    [category_description] => Semiconductor Intellectual Property
    [cat_name] => IP
    [category_nicename] => ip
    [category_parent] => 0
    [is_post] => 
)

EDAC Game of Thrones: Bob Smith is the New Executive Director

EDAC Game of Thrones: Bob Smith is the New Executive Director
by Paul McLellan on 05-15-2015 at 7:00 am

Bob Smith has been appointed executive director of EDAC, following the retirement of Bob Gardner after nearly 20 years. Bob (Smith) was most recently the marketing and business development VP for Uniquify. However, he has been in the industry for a long time with stints at IKOS, Synopsys, LogicVision and Magma. He has even been … Read More


ARM A57 (A53) Virtualizer + IP Accelerated = ?

ARM A57 (A53) Virtualizer + IP Accelerated = ?
by Eric Esteve on 05-12-2015 at 12:00 pm

Hybrid IP Prototyping Kit from Synopsys!
Synopsys has launched IP Accelerated initiative last year. The goal was clearly to accelerate Time-To-Market by providing a complete set of “tools” to augment design productivity:

  • IP Prototyping Kit with reference designs work out-of-the-box
  • IP software development kits enable early
Read More

Is Low Power a Challenge? ICE-Grain Answers the Challenge

Is Low Power a Challenge? ICE-Grain Answers the Challenge
by Paul McLellan on 05-12-2015 at 7:00 am

Blogs have limited wordcount so insert your own generic opening paragraph here about the importance of low power in IC design. Mention IoT and cloud datacenters for extra credit.

It is well-known that the biggest reductions in power come from changes at the architectural level. Tools and process can do some things and since they… Read More


Antifuse is the New Foundation of NVM Below 16nm

Antifuse is the New Foundation of NVM Below 16nm
by Paul McLellan on 05-08-2015 at 7:00 am

Today the non-volatile memory (NVM) foundation is the eFuse. It is typically available for free from the foundry and is the default choice because, like Mount Everest, it is there. However, like Mount Everest it is big. It is also power hungry and slow. eFuse solutions blow the silicide on the poly line creating a change in resistance.… Read More


Love IP Party at DAC 2015

Love IP Party at DAC 2015
by Paul McLellan on 05-06-2015 at 7:00 am

Once again there is a Heart of Technology event at DAC. It is the Love IP Party on Monday evening. Full details at the end of this entry, but first a bit of context. Heart of Technology was started by Jim Hogan who probably doesn’t need much introduction to anyone who has worked in EDA for any length of time.

I met with Jim, along with… Read More


What is Real SAMV71 DSP Performance in Auto Audio?

What is Real SAMV71 DSP Performance in Auto Audio?
by Eric Esteve on 05-06-2015 at 2:33 am

Why selecting ARM Cortex-M7 processor based Atmel SAMV70/71 for automotive entertainment application? The top three reasons are the Cortex-M7 clock speed (300 Mhz), the integration of a floating point (FPU) DSP and, last but not least because Atmel SAMV70/71 has obtained automotive qualification. If you dig into SAMV70/71… Read More


What is Real SAMV71 DSP Performance in Auto Audio?

What is Real SAMV71 DSP Performance in Auto Audio?
by Eric Esteve on 05-06-2015 at 2:33 am

Why selecting ARM Cortex-M7 processor based Atmel SAMV70/71 for automotive entertainment application? The top three reasons are the Cortex-M7 clock speed (300 Mhz), the integration of a floating point (FPU) DSP and, last but not least because Atmel SAMV70/71 has obtained automotive qualification. If you dig into SAMV70/71… Read More


TSMC 10nm Readiness and 3DIC

TSMC 10nm Readiness and 3DIC
by Paul McLellan on 05-03-2015 at 1:00 am

At the TSMC Technology Symposium last month Suk Lee presented a lot of information on design enablement. Suk is an interesting guy with a unique background in ASIC, Semiconductor, EDA, and now Foundry. In baseball terms that would be like playing infield, outfield, home plate, and umpire!

Around the turn of the millennium Suk actually… Read More


Automating Timing Closure Using Interconnect IP, Physical Information

Automating Timing Closure Using Interconnect IP, Physical Information
by Majeed Ahmad on 04-29-2015 at 1:00 pm

Timing closure is a “tortoise” for some system-on-chip (SoC) designers just the way many digital guys call RF design a “black art”. Chip designers often tell horror stories of doing up to 20 back-end physical synthesis place & route (SP&R) iterations with each iteration taking a week or more. “Timing closure”, a largely… Read More


The 2015 DAC Designer and IP Track

The 2015 DAC Designer and IP Track
by Anne Cirkel on 04-27-2015 at 8:00 pm

What an exciting year for DAC with record submissions in nearly every category. Most impressive is the increase in Designer and IP Track submissions, content that is helping to continue to evolve and improve the show. If you haven’t already registered, why not do so now?

A brief bit of background about the conference: DAC’s roots… Read More