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FPGA
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Insights from the Next FPGA Platform Event

Insights from the Next FPGA Platform Event
by Daniel Nenni on 02-11-2020 at 10:00 am
Categories: Achronix, eFPGA, FPGA

The Next FPGA Platform SemiWiki

Unfortunately, I missed this event since I was in China. Fortunately, Manoj Roge VP Strategic Planning and Business Development at Achronix participated and did a nice write-up. Manoj has more than 20 years of experience in the programable business with Cypress Semiconductor, Xilinx, Altera, and now Achronix so you should definitely… Read More

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WEBINAR: Prototyping With Intel’s New 80M Gate FPGA

WEBINAR: Prototyping With Intel’s New 80M Gate FPGA
by Daniel Nenni on 01-29-2020 at 10:00 am
Categories: FPGA, Intel, Prototyping, S2C EDA, Xilinx

The next generation FPGAs have been announced, and they are BIG!  Intel is shipping its Stratix 10 GX 10M FPGA, and Xilinx has announced its VU19P FPGA for general availability in the Fall of next year.  The former is expected to support about 80M ASIC gates, and the latter about 50M ASIC gates.  And, to bring this mind-boggling gate… Read More

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Network on Chip Brings Big Benefits to FPGAs

Network on Chip Brings Big Benefits to FPGAs
by Tom Simon on 12-19-2019 at 10:00 am
Categories: Achronix, AI, eFPGA, FPGA

NAPs provide connection to high speed NoC

The conventional thinking about programmable solutions such as FPGAs is that you have to be willing to make a lot of trade-offs for their flexibility. This has certainly been the case in many instances. Even just getting data across the chip can eat up valuable routing resources and add a lot of overhead. These problems are exacerbated… Read More

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New Generation of FPGA Based Distributed Accelerator Cards Offer High Performance and Adaptability

New Generation of FPGA Based Distributed Accelerator Cards Offer High Performance and Adaptability
by Tom Simon on 12-05-2019 at 10:00 am
Categories: Achronix, AI, eFPGA, FPGA, IP

Achronix FPGA used on BittWare Accelerator Card

We have learned from nature that two characteristics are helpful for success, diversity and adaptability. The same has been shown to be true for computing systems. Things have come a long way from when CPU centric computing was the only choice. Much heavy lifting these days is done by GPUs, ASICs, and FPGAs, with CPUs in a support … Read More

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Achronix Announces New Accelerator Card at Linley Fall Processor Conference – VectorPath

Achronix Announces New Accelerator Card at Linley Fall Processor Conference – VectorPath
by Randy Smith on 11-04-2019 at 10:00 am
Categories: Achronix, eFPGA, Events, FPGA

This blog is my second blog from this year’s Linley Fall Processor Conference. The first two blogs focused on edge inference solutions. Achronix’s discussion was much broader than just AI/ML; it was about where FPGA’s have been going and culminated with a product announcement preview. I’ll get to the announcement in a moment, … Read More

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Design Perspectives on Intermittent Faults

Design Perspectives on Intermittent Faults
by Bernard Murphy on 10-08-2019 at 5:00 am
Categories: EDA, FPGA, Synopsys

Faults

Bugs are an inescapable reality in any but the most trivial designs and usually trace back to very deterministic causes – a misunderstanding of the intended spec or an incompletely thought-through implementation of some feature, either way leading to reliably reproducible failure under the right circumstances. You run diagnostics,… Read More

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Acceleration in a Heterogenous Compute Environment

Acceleration in a Heterogenous Compute Environment
by Bernard Murphy on 10-02-2019 at 5:00 am
Categories: eFPGA, FPGA
3 Comments

Acceleration

Heterogenous compute isn’t a new concept. We’ve had it in phones and datacenters for quite a while – CPUs complemented by GPUs, DSPs and perhaps other specialized processors. But each of these compute engines has a very specific role, each driven by its own software (or training in the case of AI accelerators). You write software… Read More

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Xilinx on ANSYS Elastic Compute for Timing and EM/IR

Xilinx on ANSYS Elastic Compute for Timing and EM/IR
by Bernard Murphy on 08-20-2019 at 5:00 am
Categories: Ansys, Inc., EDA, FPGA, Xilinx

RedHawk-SC

I’m a fan of getting customer reality checks on advanced design technologies. This is not so much because vendors put the best possible spin on their product capabilities; of course they do (within reason), as does every other company aiming to stay in business. But application by customers on real designs often shows lower performance,… Read More

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Tortuga Webinar: Ensuring System Level Security Through HW/SW Verification

Tortuga Webinar: Ensuring System Level Security Through HW/SW Verification
by Bernard Murphy on 08-08-2019 at 6:00 am
Categories: Cadence, Events, Security, Synopsys, Tortuga Logic, Xilinx

Jason Oberg

We all know (I hope) that security is important so we’re willing to invest time and money in this area but there are a couple of problems. First there’s no point in making your design secure if it’s not competitive and making it competitive is hard enough, so the great majority of resource and investment is going to go into that objective.… Read More

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An AI Accelerator Ecosystem For High-Level Synthesis

An AI Accelerator Ecosystem For High-Level Synthesis
by Bernard Murphy on 07-01-2019 at 10:00 am
Categories: AI, EDA, FPGA, Siemens EDA
1 Comment

AI accelerators as engines for object or speech recognition (among many possibilities), are becoming increasingly popular for inference in mobile and power-constrained applications. Today much of this inferencing runs largely in software on CPUs or GPUs thanks to the sheer size of the smartphone market, but that will shift… Read More