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80% of specification optimization and almost 100% of the performance/power trade-offs can be achieved during architecture exploration of product design. RISC-V offers a huge opportunity with lots of pipeline and instruction set enhancement opportunities. Can it really attain the utopian success that people are looking… Read More
Previous SemiWiki articles have discussed the introduction of embedded Spin-Transfer Torque Magnetoresistive RAM IP from GLOBALFOUNDRIES, as an evolution replacement for non-volatile embedded flash memory. (link, link)
Those articles described the key features of STT-MRAM technology, but didn’t delve into a key reliability… Read More
I had the opportunity to speak with Pete Rodriguez and Alain Labat in regards to the upcoming webinar on M&A. I have worked with both Pete and Alain in the past so I can tell you personally that this event will be well worth your time. This is truly an all star cast with a collective experience base with billions of dollars worth of … Read More
The emergence of 2.5D heterogeneous die integration using a silicon (or organic) interposer has enabled unique system architectures. The term “More than Moore” has been used to describe the circuit density and cost advantages of leveraging multiple die in the package, the die potentially in different process technologies. … Read More
The causes of the chip shortage crisis have been widely discussed, but what about specific solutions? How can semiconductor manufacturers add new capacity to meet demand as quickly as possible?
While there is a lot of talk about investment in building new chip plants, these traditional methods of manufacturing capacity growth… Read More
At the 2021 VLSI Technology Symposium, Imec presented on Ruthenium (Ru) and Molybdenum (Mo) as alternate Word Line (WL) materials for 3D NAND Flash “First Demonstration of Ruthenium and Molybdenum Word lines Integrated into 40nm Pitch 3D NAND Memory Devices”. I had an opportunity to interview one of the authors: Maarten Rosmeulen.… Read More
The annual VLSI Symposium provides unique insights into R&D innovations in both circuits and technology. Indeed, the papers presented are divided into two main tracks – Circuits and Technology. In addition, the symposium offers workshops, forums, and short courses, providing a breadth of additional information.
At… Read More
FinFETs devices are reaching their limits for scaling. Horizontal Nanosheets (HNS) are a type of Gate All Around (GAA) device that offers better scaling and performance per unit area. HNS is the logical next step from FinFETs because HNS processing is similar to FinFETs with a limited number of process changes required.
At the … Read More
At Veriest we host VERIFICATION MEETUPS periodically to share verification wisdom. In our virtual meetings we’ve had hundreds of attendants from the US, Europe, Israel, India, and China. Most recently we were able to host a live event in Israel – I want to share feedback from that meeting.
We started with two presentations:… Read More
At the 2021 Symposium on VLSI Technology and Circuits in June a short course was held on “Advanced Process and Devices Technology Toward 2nm-CMOS and Emerging Memory”. In this article I will review the first two presentations covering leading edge logic devices. The two presentations are complementary and provide and excellent… Read More
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Available Is Not In Control: Balancing Output, Quality, and Risk in High-Volume Fabs