SiC Forum2025 8 Static v3
WP_Term Object
(
    [term_id] => 50
    [name] => Events
    [slug] => events
    [term_group] => 0
    [term_taxonomy_id] => 50
    [taxonomy] => category
    [description] => 
    [parent] => 0
    [count] => 1444
    [filter] => raw
    [cat_ID] => 50
    [category_count] => 1444
    [category_description] => 
    [cat_name] => Events
    [category_nicename] => events
    [category_parent] => 0
    [is_post] => 
)

Numerical Sizing and Tuning Shortens Analog Design Cycles

Numerical Sizing and Tuning Shortens Analog Design Cycles
by Tom Simon on 11-22-2021 at 6:00 am

Sizing and tuning

By any measure analog circuit design is a difficult and complex process. This point is driven home in a recent webinar by MunEDA. Michael Pronath, VP Products and Solutions at MunEDA, lays out why, even with the assistance of simulators, analog circuit sizing and tuning can consume weeks of time in what can potentially be a non-convergent… Read More


Taiwan Semiconductor Outlook May 1988

Taiwan Semiconductor Outlook May 1988
by Daniel Nenni on 11-12-2021 at 6:00 am

James E. Dykes

This is an interesting piece of TSMC history. From 1987 to 1988 James E. Dykes served as the first President and Chief Executive Officer of Taiwan Semiconductor Manufacturing Company Ltd.

Taiwan Semiconductor Outlook
by James E. Dykes
President & Chief Executive Officer
Taiwan Semiconductor Manufacturing Company

Given… Read More


Cliosoft Webinar: What’s Needed for Next Generation IP-Based Digital Design

Cliosoft Webinar: What’s Needed for Next Generation IP-Based Digital Design
by Mike Gianfagna on 11-04-2021 at 10:00 am

Cliosoft Webinar Whats Needed for Next Generation IP Based Digital Design

There’s plenty of talk about requirements for IP data management. The fundamental methods to prevent chaos, waste or worse are popular topics. I’ve covered webinars from Cliosoft on the topic on SemiWiki. But what about the future? What’s really needed to set up a path that scales, addressing the challenges of today and the new … Read More


Alchip Reveals How to Extend Moore’s Law at TSMC OIP Ecosystem Forum

Alchip Reveals How to Extend Moore’s Law at TSMC OIP Ecosystem Forum
by Mike Gianfagna on 11-03-2021 at 10:00 am

Alchip Reveals How to Extend Moores Law at TSMC OIP Ecosystem Forum

The TSMC Open Innovation Platform (OIP) event brings together a wide array of companies reporting cutting edge work that are part of TSMC’s rather substantial ecosystem. The event covers everything from high-performance computing to mobile, automotive, IoT, RF and 3D IC design. Of particular interest for this post is a presentation… Read More


Update on TSMC’s 3D Fabric Technology

Update on TSMC’s 3D Fabric Technology
by Tom Dillinger on 11-03-2021 at 8:00 am

3D eTV testchip

TSMC recently held their 10th annual Open Innovation Platform (OIP) Ecosystem Forum.  An earlier article summarized the highlights of the keynote presentation from L.C. Lu, TSMC Fellow and Vice-President, Design and Technology Platform, entitled “TSMC and Its Ecosystem for Innovation” (link).

Overview of 3D Fabric

The TSMC… Read More


Design Technology Co-Optimization for TSMC’s N3HPC Process

Design Technology Co-Optimization for TSMC’s N3HPC Process
by Tom Dillinger on 11-02-2021 at 8:00 am

N3HPC performance comparison

TSMC recently held their 10th annual Open Innovation Platform (OIP) Ecosystem Forum.  An earlier article summarized the highlights of the keynote presentation from L.C. Lu, TSMC Fellow and Vice-President, Design and Technology Platform, entitled “TSMC and Its Ecosystem for Innovation” (link).

One of the topics that L.C. … Read More


Highlights of the TSMC Open Innovation Platform Ecosystem Forum

Highlights of the TSMC Open Innovation Platform Ecosystem Forum
by Tom Dillinger on 11-01-2021 at 8:00 am

N3 comparison

TSMC recently held their 10th annual Open Innovation Platform (OIP) Ecosystem forum.  The talks included a technology and design enablement update from TSMC, as well as specific presentations from OIP partners on the results of recent collaborations with TSMC.  This article summarizes the highlights of the TSMC keynote from… Read More


Webinar: A Practical Approach to FinFET Layout Automation That Really Works

Webinar: A Practical Approach to FinFET Layout Automation That Really Works
by Mike Gianfagna on 10-27-2021 at 10:00 am

Webina A Practical Approach to FinFET Layout Automation That Really Works

There are certain tasks that have been the holy grail of EDA for some time. A real silicon compiler – high level language as input and an optimal, correct layout as output is one. Fully automated analog design – objectives as input, optimal circuit as output is another. With the increased layout times, due to the ever-increasing design… Read More


Take the Achronix Speedster7t FPGA for a Test Drive in the Lab

Take the Achronix Speedster7t FPGA for a Test Drive in the Lab
by Mike Gianfagna on 10-19-2021 at 10:00 am

Take the Achronix Speedster7t FPGA for a Test Drive in the Lab

Achronix is known for its high-performance FPGA solutions. In this post, I’ll explore the Speedster7T FPGA. This FPGA family is optimized for high-bandwidth workloads and eliminates performance bottlenecks with an innovative architecture. Built on TSMC’s 7nm FinFET process, the family delivers ASIC-level performance … Read More


IEDM 2021 – Back to in Person

IEDM 2021 – Back to in Person
by Scotten Jones on 10-18-2021 at 6:00 am

IEDM 2021 SemiWIki

Anyone who has read my previous articles about IEDM knows I consider it the premier conference on process technology.

Last year due to COVID IEDM was virtual and although virtual offers some advantages the hallway conversations that can be such an important part of the conference are lost. This year IEDM is returning as a live event… Read More