My beautiful wife and I attended the annual Global Semiconductor Alliance (GSA) Awards event last week. Usually this is a solo event but since my wife is CFO of SemiWiki I was able to get her an invite. I go every year and she wanted to see what all of the excitement was about. She also knows quite a few industry people from attending the… Read More
WEBINAR: FPGA-Accelerated AI Speech Recognition
The three-step conversational AI (CAI) process – automatic speech recognition (ASR), natural language processing, and text-to-synthesized speech response – is now deeply embedded in the user experience for smartphones, smart speakers, and other devices. More powerful large language models (LLMs) can answer more queries… Read More
WEBINAR: Joint Pre synthesis RTL & Power Intent Assembly flow for Large System on Chips and Subsystems
Nowadays, low power design requirements are key for large SoCs (system on chips) for different applications: AI, Mobile, HPC, etc. Power intent management early in the design flow is becoming crucial to help facing PPA (Power Performance Area) design challenges.
With the increasing complexity of such … Read More
IEDM Buzz – Intel Previews New Vertical Transistor Scaling Innovation
For more than 65 years, the IEEE International Electron Devices Meeting (IEDM) has been the world’s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. As I post this, the conference is underway in San Francisco… Read More
Webinar: “Navigating our AI Wonderland” … with humans-in-the-Loop?
AI is here, there, and absolutely everywhere – now and forever.
The electronics industry, and the world at-large, have experienced an overwhelming amount of AI coverage this year, with no letup in store for 2024. Both EE Times and Silicon Catalyst have recently staged events around artificial intelligence:
- “AI Everywhere” delivered
RISC-V Summit Buzz – Axiomise Accelerates RISC-V Designs with Next Generation formalISA®
If the recent RISC-V Summit proved one thing it’s that open-source hardware design, and particularly the RISC-V instruction set architecture (ISA) has entered the mainstream. It is a design methodology and architecture to watch closely. Across a broad range of applications from data center, to automotive, to IoT, RISC-V processors… Read More
RISC-V Summit Buzz – Semidynamics Founder and CEO Roger Espasa Introduces Extreme Customization
Founded in 2016 and based in Barcelona, Spain, Semidynamics™ is the only provider of fully customizable RISC-V processor IP. The company delivers high bandwidth, high performance cores with vector units and tensor units targeted at machine learning and AI applications. There were some recent announcements from Semidynamics… Read More
WEBINAR : Avoiding Metastability in Hardware Software Interface (HSI) using CDC Techniques
This webinar looks at the challenges a Design Engineer could face, such as when various IP blocks within an SoC are required to work in different clock domains to satisfy the power constraints.
Abstract:
Various IP blocks within an SoC are often required to work in different clock domains in order to satisfy the power constraints.… Read More
Siemens Digital Industries Software Collaborates with AWS and Arm To Deliver an Automotive Digital Twin
According to McKinsey & Company, a digital twin is a digital representation of a physical object, person, or process, contextualized in a digital version of its environment. Digital twins can help an organization simulate real situations and their outcomes, ultimately allowing it to make better decisions. Anyone… Read More
Webinar: Silicon Catalyst & EE Times Examine the Bigger Picture Aspects of AI – Nov. 29, 2023 – 9am to 10am Pacific
Artificial Intelligence (AI) is dominating the news cycle these days. It used to be about the latest (and largest) chips to accelerate AI algorithms. While that’s still relevant and exciting, AI news is taking a much broader, socioeconomic character. What does AI mean for job security, the economy, or even life on Earth? These … Read More


The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival