Join this webinar and see UCIe in action! This webinar presents the SystemVerilog models of a Universal Chiplet Interconnect Express (UCIe) interface, including both the analog circuits in the electrical layer and digital FSMs in the logical layer. The whole physical layer (PHY) model can be efficiently simulated in SystemVerilog,… Read More
WEBINAR: Driving Forward with UWB Radar: Enhancing Child Safety in Automotive
The rapid advancement of UWB (Ultra-Wideband) wireless technology has garnered significant attention and interest, thanks to its adoption by leading smartphone brands and its versatile range of applications. Within the automotive industry, UWB has already emerged as the preferred choice for Digital Keys in the premium… Read More
WEBINAR: An Ideal Neural Processing Engine for Always-sensing Deployments
Always-sensing cameras are a relatively new method for users to interact with their smartphones, home appliances, and other consumer devices. Like always-listening audio-based Siri and Alexa, always-sensing cameras enable a seamless, more natural user experience. However, always-sensing camera subsystems require specialized… Read More
AMAT- Trailing Edge & China Almost Offset Floundering Foundry & Missing Memory
-AMAT reported inline resulted helped by trailing edge & China
-Memory remains at very low levels- Foundry remains uninspiring
-China seems to be buying anything they are allowed to buy
-The recovery is too far out & unknown to handicap
Quarter was OK and Guidance also OK
Revenue was $6.63B and EPS of $1.86 versus reduced… Read More
Chiplet Q&A with John Lee of Ansys
At the recent Synopsys Users Group Meeting (SNUG) I had the honor of leading a panel of experts on the topic of chiplets. One of those panelists was John Lee, Head of Electronics, Semiconductors and Optics at Ansys.
How is the signoff flow evolving and what is being done to help mitigate the growing signoff complexity challenge?
With… Read More
SPIE 2023 – imec Preparing for High-NA EUV
The SPIE Advanced Lithography Conference was held in February. I recently had the opportunity to interview Steven Scheer, vice president of advanced patterning process and materials at imec and review selected papers that imec presented.
I asked Steve what the overarching message was at SPIE this year, he said readiness for … Read More
Join the AI Generated Open-Source Silicon Design Challenge!
As we all know design starts are the life blood of the semiconductor industry, both big and small. Enabling those design starts is what the semiconductor ecosystem is all about and Efabless has a very unique value proposition in this regard.
Efabless is a free cloud-based chip design platform, growing community of 9000+ chip designers,… Read More
Emerging Stronger from the Downturn
It was refreshing to hear a talk focused on emerging stronger from the downturn when the news and media are focused on the gloom. At the recent Siemens EDA User2User conference, Joe Sawicki, executive vice president, IC, gave an uplifting keynote talk to the audience. He highlighted a secular growth trend happening in the semiconductor… Read More
SEMI ESD Alliance CEO Outlook Sponsored by Keysight Promises Industry Perspectives, Insights
Spring wouldn’t be the same without an opportunity to hear from some of the most visible executives of electronic system design (ESD) market segment. The in-person CEO Outlook sponsored by Keysight and hosted by the ESD Alliance, a SEMI Technology Community, will be held Thursday, May 18, in Santa Clara, Calif.
Attendees can expect… Read More
Silicon Catalyst and Arm announce $150,000 Silicon Startup Contest!
As I sift through mounds of semiconductor press releases trying to figure out the relevance (with mixed results) I consider it a learning experience even when they don’t really tell me anything. This one however tells me two very important things:
1) Arm is a much more competitive company with the new leadership. I saw a noticeable… Read More


AI RTL Generation versus AI RTL Verification