WP_Term Object
(
    [term_id] => 14
    [name] => Synopsys
    [slug] => synopsys
    [term_group] => 0
    [term_taxonomy_id] => 14
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 698
    [filter] => raw
    [cat_ID] => 14
    [category_count] => 698
    [category_description] => 
    [cat_name] => Synopsys
    [category_nicename] => synopsys
    [category_parent] => 157
    [is_post] => 
)
800x100 Efficient and Robust Memory Verification 
WP_Term Object
(
    [term_id] => 14
    [name] => Synopsys
    [slug] => synopsys
    [term_group] => 0
    [term_taxonomy_id] => 14
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 698
    [filter] => raw
    [cat_ID] => 14
    [category_count] => 698
    [category_description] => 
    [cat_name] => Synopsys
    [category_nicename] => synopsys
    [category_parent] => 157
    [is_post] => 
)
Synopsys
Posted on

Circuit Simulation Panel Discussion at #53DAC

Circuit Simulation Panel Discussion at #53DAC
by Daniel Payne on 06-29-2016 at 12:00 pm
Categories: EDA, Events, FinFET, Synopsys, TSMC

Four panelists from big-name semiconductor design companies spoke about their circuit simulation experiences at #53DAC in Austin this year, so I attended to learn more about SPICE and Fast SPICE circuit simulation. I heard from the following four companies:… Read More

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TMR approaches should vary by FPGA type

TMR approaches should vary by FPGA type
by Don Dingee on 06-20-2016 at 4:00 pm
Categories: EDA, FPGA, Synopsys

We’ve introduced the concepts behind triple modular redundancy (TMR) before, using built-in capability in Synopsys Synplify Premier to synthesize TMR circuitry into FPGAs automatically. A recent white paper authored by Angela Sutton revisits the subject… Read More

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Custom IC Layout Design at #53DAC

Custom IC Layout Design at #53DAC
by Daniel Payne on 06-17-2016 at 12:00 pm
Categories: EDA, Synopsys

Last week at the #53DAC conference there was a lot of excitement in the air about custom IC design, especially at the luncheon that I attended on Tuesday from Synopsys where they had customers like STMicroelectronics, GSI Technology, Samsung Foundry and the Synopsys IP group talk about their experiences using the new Custom Compiler… Read More

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One FPGA synthesis flow for different IP types

One FPGA synthesis flow for different IP types
by Don Dingee on 05-06-2016 at 4:00 pm
Categories: EDA, FPGA, Synopsys

Both Altera and Xilinx are innovative companies with robust ecosystems, right? It would be a terrible shame if you located the perfect FPGA IP block for a design, but couldn’t use it because it was in the “wrong” format for your preferred FPGA. What if there were a way around that?

There is a compelling argument to use each FPGA vendor’s… Read More

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Are Standard Cell Libs, Memories and Mixed-signal IP Availabe at 7nm FF?

Are Standard Cell Libs, Memories and Mixed-signal IP Availabe at 7nm FF?
by Eric Esteve on 05-05-2016 at 7:00 am
Categories: EDA, FinFET, IP, Synopsys

More than 500 designers (562) have responded to a survey made in 2015 by Synopsys. Answering to the question “What is the fastest clock speed of your design?” 56% have mentioned a clock higher than 500 MHz (and still 40% higher than 1 GHz). If you compare with the results obtained 10 years ago, the largest proportion of answers was for… Read More

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Bringing Formal Verification into Mainstream

Bringing Formal Verification into Mainstream
by Pawan Fangaria on 04-28-2016 at 7:00 am
Categories: EDA, Synopsys

Formal verification can provide a large productivity gain in discovering, analyzing, and debugging complex problems buried deep in a design, which may be suspected but not clearly visible or identifiable by other verification methods. However, use of formal verification methods hasn’t been common due to its perceived complexity… Read More

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SpyGlass DFT ADV accelerates test closure – Xilinx and Synopsys webinar

SpyGlass DFT ADV accelerates test closure – Xilinx and Synopsys webinar
by Bernard Murphy on 04-26-2016 at 12:00 pm
Categories: EDA, Synopsys, Xilinx

Fed up with ECOing your way out of test problems? You might want to register for this webinar.When you’re building monster SoC FPGAs, you have all the same problems you have with any other SoC. That includes getting to very high test coverage as quickly as you can with a design targeted to the most advanced processes. We’re not just … Read More

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Static Timing Analysis Keeps Pace with FinFET

Static Timing Analysis Keeps Pace with FinFET
by Daniel Payne on 04-22-2016 at 12:00 pm
Categories: EDA, FinFET, Synopsys

At SemiWiki we’ve been blogging for several years now on the semiconductor design challenges of FinFET technology and how it requires new software approaches to help chip designers answer fundamental questions about timing, power, area and design closure. When you mention the phrase Static Timing Analysis (STA) probably… Read More

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Debugging is the whole point of prototyping

Debugging is the whole point of prototyping
by Don Dingee on 04-15-2016 at 4:00 pm
Categories: EDA, Synopsys

The prototype is obviously the end goal of FPGA-based prototyping, however success of the journey relies on how quickly defects can be found and rectified. Winning in the debug phase involves a combination of methodology, capability, and planning. Synopsys recently aired a webinar on their HAPS environment and its debug ecosystem.… Read More

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Custom Layout Productivity Gets a Boost

Custom Layout Productivity Gets a Boost
by Tom Dillinger on 04-11-2016 at 7:00 am
Categories: EDA, Synopsys

In the 1970’s, when Moore’s Law was still in its infancy, Bill Lattin from Intel published a landmark paper [1]. In it he identified the need for new design tools and methods to improve layout productivity, which he defined as the drawn and verified number of transistors per day per layout designer. He said existing … Read More