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I talked to Michael Buehler-Garcia about the changes Mentor is making to U2U, their user conference. It is in San Jose on April 25th at the DoubleTree.
Firstly, there are 3 great keynotes, two of whom I’ve seen speak before and can unreservedly recommend. Unfortunately I’m traveling that week and won’t be able… Read More
It appears that immersion lithography is now the plan of record for manufacturing ICs at 14nm. How is it possible to use 193nm wavelength light at 14nm? How can we provide the process window to pattern the such tight pitches? The secret lies in computational lithography. For 20nm, the two key innovations in computational lithography… Read More
April 25, 2013, San Jose, CA
Click here to register.
Come hear Mentor Graphics CEO, Wally Rhines, 2013 Kaufman Award Winner,Chenming Hu, and Xilinx Senior VP,Victor Peng, at the User2User Conference in San Jose.
KEYNOTES
Organizing by Design
9:00am – 9:50am
Walden C. Rhines | CEO & Chairman | Mentor Graphics
Winning products… Read More
I recently spoke to Arvind Narayanan, Product Marketing Manager for Mentor’s place and route division about emerging technology. This of course led to FinFETS, FDSOI, performance, power, and cost-benefit. The battle between FDSOI and FinFETs, said Narayanan, is going to be something to watch.
Both FDSOI and FinFET technologies… Read More
Ground. It’s that little downward-pointing triangle that somehow works miracles on every schematic. It looks very simple until one has to tackle modern power distribution network (PDN) design on a board with high speed and high power draw components, and you soon discover ground is a complicated fairy tale with a lot of influences.… Read More
TSMC will host their annual technology symposium at several locations in the U.S. on April 9th in San Jose, April 16th in Austin, and April 23rd in Boston. TSMC will discuss the market outlook, design enablement, and technology for high-speed computing, mobile communications, connectivity and storage, CIS, embedded flash, … Read More
Amidst frequently changing requirements, time pressure and demand for high accuracy, it is imperative that EDA and design companies look at time consuming processes in the overall design flow and find alternatives without losing accuracy. High Frequency Analysis of IC designs is one such process which is traditionally based… Read More
This year’s Mentor Graphics user group meeting, User2User, will be held at the DoubleTree by Hilton in San Jose, California on April 25, 2013. The featured keynote presenters include…
Yesterday evening was the annual EDAC CEO forecast meeting. Actually it is not really a forecast meeting any more, more a sort of CEO response to some survey questions asked of EDAC members. Rich Valera of Needham moderated with Lip-Bu, Aart and Wally, along with Simon Segars representing the IP arm(!) of the business and Raul Camposano… Read More
What: Better IP Test with IJTAG
When: 26 March, 2013, 10:30am-1:30pm
Where: Mentor Graphics, 46871 Bayside Parkway, Fremont, CA 94538
If you are involved in IC test*, you’ve probably heard about the IEEE P1687 standard, called IJTAG for ‘internal’ JTAG. IJTAG defines a standard for embedded IP that includes simple… Read More
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