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Addressing SoC Test Implementation Time and Costs

Addressing SoC Test Implementation Time and Costs
by Daniel Payne on 04-20-2021 at 10:00 am

testmax flow

In business we all have heard the maxim, “Time is Money.” I learned this lesson early on in my semiconductor career when doing DRAM design, discovering that the packaging costs and time on the tester were actually higher than the fabrication costs. System companies like IBM were early adopters of Design For Test (DFT)… Read More


Your Car Is a Smartphone on Wheels—and It Needs Smartphone Security

Your Car Is a Smartphone on Wheels—and It Needs Smartphone Security
by Taylor Armerding on 04-18-2021 at 10:00 am

Your Car Is a Smartphone on Wheels—and It Needs Smartphone Security

Your modern car is a computer on wheels—potentially hundreds of computers on a set of wheels. Heck, even the wheels are infested with computers—what do you think prompts that little light on your dashboard to come on if your tire pressure is low? And computers don’t just run your infotainment system, backup camera, dashboard warning

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Why I made the world’s first on-demand formal verification course

Why I made the world’s first on-demand formal verification course
by Ashish Darbari on 04-18-2021 at 6:00 am

formal use model 2


Verification Challenge
As chip design complexity continues to grow astronomically with hardware accelerators running riot with the traditional hardware comprising CPUs, GPUs, networking and video and vision hardware, concurrency, control and coherency will dominate the landscape of verification complexity for safe … Read More


Podcast EP16: Hyperscale Computing & Changes in the Datacenter

Podcast EP16: Hyperscale Computing & Changes in the Datacenter
by Daniel Nenni on 04-16-2021 at 10:00 am

Dan is joined by Frank Schirrmeister, senior group director of solutions marketing at Cadence Design Systems, Frank has extensive experience in complex system design from his work at companies such as Cadence, Synopsys, Imperas and ChipVision. He has also advised Vayavya Labs and CriticalBlue.

Dan and Frank discuss the many… Read More


Global Variation and Its Impact on Time-to-Market for Designs

Global Variation and Its Impact on Time-to-Market for Designs
by umangdoshi on 04-14-2021 at 2:00 pm

Impact of Global Variation on Delay

We have come a long way from the days of limited and manageable characterization databases with fewer views and smaller library sizes. The technologies we are headed towards pushing characterization to its limits with special modeling for variation, aging and reliability all on a single process, voltage and temperature (PVT).… Read More


Siemens EDA Updates, Completes Its Hardware-Assisted Verification Portfolio

Siemens EDA Updates, Completes Its Hardware-Assisted Verification Portfolio
by Bernard Murphy on 04-14-2021 at 6:00 am

Siemens Hardware assisted Verification platform launch graphic 2 32521 min

Siemens EDA’s Veloce emulation products are long-established and worthy contenders in any emulation smack-down. But there was always a hole in the complete acceleration story. Where was the FPGA prototyper? Current practice requires emulation for fast simulation with hardware debug, plus prototyping for faster simulation… Read More


How PCI Express 6.0 Can Enhance Bandwidth-Hungry High-Performance Computing SoCs

How PCI Express 6.0 Can Enhance Bandwidth-Hungry High-Performance Computing SoCs
by gruggles on 04-12-2021 at 2:00 pm

How PCI Express 6.0 Can Enhance Bandwidth Hungry High Performance Computing SoCs

What do genome sequencing, engineering modeling and simulation, and big data analytics have in common? They’re all bandwidth-hungry applications with complex data workloads. High-performance computing (HPC) systems deliver the parallel processing capabilities to generate detailed and valuable insights from these applications.

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Meeting the Need for Hardware-Assisted Verification

Meeting the Need for Hardware-Assisted Verification
by Lauro Rizzatti on 04-12-2021 at 6:00 am

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Editor’s Note: Siemens EDA recently introduced a comprehensive hardware-assisted verification system comprised of hardware, software and system verification that streamlines and optimizes verification cycles while helping reduce verification cost. What follows is an edited version of an interview Verification Expert… Read More


Cadence Dynamic Duo Upgrade Debuts

Cadence Dynamic Duo Upgrade Debuts
by Bernard Murphy on 04-08-2021 at 6:00 am

Dynamic Duo min

Cadence calls their hardware acceleration platforms, Palladium Z2 for fast pre-silicon hardware debug and Protium X2 for fast pre-silicon software validation, their Dynamic Duo. With good reason. Hardware acceleration is now fundamental to managing the complexity of verification and validation for large systems, hardware… Read More


Webinar: Annapurna Labs and Altair Team up for Rapid Chip Design in the Cloud

Webinar: Annapurna Labs and Altair Team up for Rapid Chip Design in the Cloud
by Mike Gianfagna on 04-07-2021 at 6:00 am

Annapurna Labs and Altair Team up for Rapid Chip Design in the Cloud

This is a story of strategic recursion. Yes, a fancy term. I just made up. If you’re not into algorithm development you can Google recursion, but the simple explanation is we’re talking about using the cloud to design the cloud. The story begins with Annapurna Labs, a fabless chip company focused on bringing innovation to cloud infrastructure,… Read More